Need help with a Simulink model (Type 2 PLL)

Hi, MathWorks / MATLAB / Simulink community! I have recently started working my way through the "Software Defined Radio using MATLAB & Simulink and the RTL-SDR" book, and I am wondering if anybody out there would be interested and have time to help me review some of my work on the exercises. Specifically, I'm currently working "Exercise 7.9 - Challenge: Design of a Type 2 PLL" and I am not convinced that my implementation is correct, but I'm having some trouble with debugging as I'm still learning MATLAB and Simulink. I am getting a flat error of 0 right from time 0, which I was not expecting.

Is anyone interested and have time to review my implementation and give some feedback? I'd definitely appreciate it. I am attaching the Simulink and MATLAB files.

Thanks!

Shaun Lippy Middleburg, VA, USA

Answer 1

[Tyler]

Hi Harry,

I know this question is about 3 years old, but the main issue with your design is that the PLL is not reaching phaselock (which is why the error appears to be staying at around the 0 point).The reason why the PLL isn't reaching phase lock during the simulation time is because your reference frequency of 1 kHz deviates too much from the expected (quiescent) frequency of 800 Hz. For example, if you set the reference frequency to something like 805 Hz, then the PLL will reach phase lock at around ~3.5 seconds (takes a few seconds due to the small noise bandwidth).

Hope this helps!

Tyler

[Harry]

Thanks, Tyler! I appreciate the response, and it makes sense. I'm going to go back and try out your suggestions.