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Pham Van Dung
on 22 Nov 2012
Commented: Pham Van Dung
on 18 Dec 2018
Dear friends, I have an error when I try to convert StateFlow Block to Verilog: * Failed network:propagateClockRate:ratesDontMatch: When propagating rates on , signal *
Anybody can help me!
Thanks you so much!
Pham Van Dung
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imane RGUIB
on 18 Dec 2018
Hello, Pham Van Dung and Kiran Kintali, I have the same error while trying to make an IP core generation of my design, comprising a stateflow chart, using the HDL workflow advisor:
Could not apply model's setting to the Target Interface Table in Task 1.2 of the HDL Workflow Advisor for the following reason:
network:propagateClockRate:ratesDontMatch: When propagating rates on <Network CtxName="slaveV2" RefNum="n1" UserName="slaveV2/SlaveI2C/Chart" RTTIClass ="class pir::Network"/>, signal <Signal CtxName="slaveV2" RefNum="s0" UserName="scl" RTTIClass ="class pir::Signal" Network="n1\> had rate 0.000000, while the trigger signal had rate 0.100000
Can you please tell me what can be the problem?
Thank you very much
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