Quantizer modelling in Simulink

I am designing a 3rd order delta sigma ADC in simulink. I use a single bit quantiser for the design since it just replicates a comparator in the actual design.

For a single bit quantizer I could use the sign block in the Simulink. But I see that single bit quantizer (B=1, ie number of levels =2) has issues such as overloading of the quantizer and instablity for higher orders. Because of this the Dynamic range is also lower.

Now, I would like to make simulations for different quantization levels other than 2, such as B=2,3,4 and 5 bits (levels 4,8,16 and 32). For this which is the optimum model from the simulink block to use? I would like a linear quantizer block.

I tried using Quantizer block, ADC Quantiser block, Scalar quantiser decoder etc. The quantizer block is fine, since I can put the quantization interval (eg: 1 for 2 levels, 0.5 for 4 levels etc..). But For higher orders I am not getting the expected results from it. When I use the ADC Quantizer block, It doesnot give different levels at the output, rather it toggles only between 2 random values (like a single bit quantiser even if I specify the number of bits to be higher than 1), though I put the Vmin=-1 and Vmax=+1, since my FS =2.

How can I modify the ADC quantizer block to behave properly for showing up multiple levels for multiple bits?

Or can I design my own quantiser block in the simulink. I could see an Scalar Quantizer Design block from the SQD tool. Should I use that to create my quantizer? I do not know how to manipulate the SQD tool boy to create a 4 level Quantizer(2 bits), to toggle between +-1, with uniform levels [-1 -0.5 0.5 1].

Please help me to find a solution

Regards

Jay

Answer 1

[Devineni Aslesha]

I am assuming that you are modeling 3rd order delta sigma ADC using uniform quantization. You can use the ‘Idealized ADC Quantizer’ block to get multiple levels for multiple bits. In the Simulink model, pass the output of ‘Sine Wave’ block to ‘Idealized ADC Quantizer’ block and in the ‘Idealized ADC Quantizer block', set Vmin to -1, Vmax to 1 and Number of Converter Bits to B (B = 1,2,3…).

The ‘Idealized ADC Quantizer’ block can be obtained from the Simulink library browser Simulink Extras->Additional Discrete.

[Jaikrishnan Mahalekshmi Sahasranamam]

Thanks Devineni,

I have currently employed a single bit quantiser. For that i just need the sign block from the simulink. Thats not an issue.

But I had to do the simulations based on multibit quantiser to see the variation. I tried using the Idealised ADC quantizer, but it didnot give promising results. Instead I used the Quantizer block , where I could specify only the interval for eg: for a 2 bit the interval is 0.5 (means the final output is in the range of +1 and -1, with levels -0.5,-1,+0.5,+1. So 2 bits or 4 levels). Similarly for 8 levels (3 bits), the interval I specifed is 0.25 and so on. These are giving better results compared to the idealised ADC quantizer block. But I am not sure why this Idealizer ADC quantizer block is not giving expected results.