Empty objectives in Design Verifier

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Lorenzo Niccolai
Lorenzo Niccolai on 2 Mar 2019
Commented: Pat Canny on 18 Mar 2019
I created a model in Simulink and i wished to prove a property using Design Verifier.
Here is a portion of the model:
img1.png
img2.png
The verification system is the following:
img3.png
Design Verifier analysis starts correctly, but it tries to validate 27 objectives instead of 1 (it seems one for each output message in the chart above)
Also those objectives seem to be empty.
Is there a way to validate only my objective?
  5 Comments
Lorenzo Niccolai
Lorenzo Niccolai on 14 Mar 2019
I managed to insert an image of a portion of the model.
The particularity is that I have only 1 proof objective in the verification subsystem, but 27 objectives in the verification process.
In the portion of model above you can see 3 + 3 = 6 message outputs; I can count exactly 26 message outputs in my model, it seems that each one causes the spawn of an objective.
I already tryed to play with Design Verifier settings without achieving nothing.
I created another project in which I use datas over messages and the issue is gone. What's up with those messages?
Pat Canny
Pat Canny on 18 Mar 2019
Hi Lorenzo,
This likely requires further digging. I don't know if we'll solve this via MATLAB Answers.

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