I'm working on a HDL project that uses several independent, asynchronous clocks. Specifically, there is an external clock for the input logic, an internal clock for processing and another external clock for the output logic.
Even though it is my understanding that asynchronous clocks can't be modelled in Simulink directly, the whole system should be contained in a single Simulink model for simulation and verification.
I think that the synchronisation logic between the different clock domains needs to be added by hand in Xilinx Vivado after code generation. I have attached a screenshot of the model's structure for clarification.
What is the best way to generate code for such a system? Is my general approach correct? How do I get HDL Coder to let me supply the different subsystems with different clocks?
Any help with this is appreciated, thanks in advance.