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How to model a system with independent clocks for HDL Code generation?

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I'm working on a HDL project that uses several independent, asynchronous clocks. Specifically, there is an external clock for the input logic, an internal clock for processing and another external clock for the output logic.
Even though it is my understanding that asynchronous clocks can't be modelled in Simulink directly, the whole system should be contained in a single Simulink model for simulation and verification.
I think that the synchronisation logic between the different clock domains needs to be added by hand in Xilinx Vivado after code generation. I have attached a screenshot of the model's structure for clarification.
What is the best way to generate code for such a system? Is my general approach correct? How do I get HDL Coder to let me supply the different subsystems with different clocks?
Any help with this is appreciated, thanks in advance.
Felix Schneider
Felix Schneider on 21 Jun 2018
Hello Garrey,
thanks for your reply.
The clock rates right now in development are 40 MHz for 1, 100 MHz for 2 and 5 MHz for 3. However, especially the output clock domain rate (3) may still be changed later in the development process and it cannot be guaranteed that there will always be a whole-number ratio between the rates. But I think that the bigger problem is the unknown phase relationship between the clocks.

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Accepted Answer

Garrey Rice
Garrey Rice on 25 Jun 2018
Hi Felix,
Thanks for the info. There are two ways to achieve this.
  1. Use a different rate in Simulink to represent each clock domain in your system, and set Clock inputs to Multiple under Model Configuration Parameters -> HDL Code Generation -> Global Settings. HDL Coder will provide a separate clock input for each rate. To generate HDL code the rates need to be related by integer factors, however you can connect up whatever you like when you instantiate the resulting HDL code. You can also use rates that are not related by integer factors for verification purposes in Simulink. See the attached example (
  2. There is also an option called “Use trigger signal as clock” under Model Configuration Parameters -> HDL Code Generation -> Global Settings -> Ports. This option allows you to explicitly represent clocks as signals in Simulink when using triggered subsystems.
Kind regards, Garrey

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