I am making a simulation off some power converters. I have my topology built with sim power system, my regulation in a triggered simulink subsystem and the modulator is in a regular subsystem. I made a basic pwm modulator as shown in picture 1. Sin wave in alfa/beta come and is converted to normal 3 phases and then compared with the carier signal.
But its not working as intended. Sometimes the "sample" rate of the carrier triangle signal drops and the "is grater" block misses a comparison. See picture 2. The problem seams to be present only at the lower amplitude of the triangle. The repeating sequence block is set up as: Time values [0 tsw/2 tsw] and output values [1 -1 1]
How do I force simulink to always generate the triangle signal to the negative amplitude?
Solver is set to variable-step, max step size 1e-4 relative tolerance 1e-4 and everything else is on auto. I have tried to use different solver and different relative tolerances, but the problem is still there or the simulation takes for ever (1 min runnin and its solved 1e-8 s).
Thank you in advance, Marko