Design Verifier error after 2 days of running analysis

I have a simple model in Simulink, which consists of a MATLAB function with inputs and outputs. The function is pretty simple, but when I run the Design Verification analysis, it runs for a long time. I initially thought it was frozen, but the fact that the clock was running made us let it run to see what happened. 

After almost 59 hours it stopped with the following error: "Analysis produced error". The error message is as follows:

Analysis Time - 58:53:41

Internal Error in Simulink Verifier back end.

An unexpected internal error occurred in Simulink Design Verifier. If you can reproduce this problem, please report it to MathWorks by copying this log contents and including the .dvo file contained in the directory:

<path of log file>

04-Dec-2016 04:05:17

Error detection produced errors.

* *

The settings used were: 

Maximum analysis time (s):Inf; 

Design Error Detection: Divide by zero.

Answer 1

[MathWorks Support Team]

This error can occur when the machine used to implement the workflow runs out of memory when performing the analysis, i.e the machine does not have enough RAM. This is most likely the reason for the internal error referred to in the error message when the analysis times out. 

A workaround would be to consider using a machine with larger memory (higher RAM), or to reduce the analysis time of the model. Sometimes, the dimensions of the data being used inside the model could also lead to significantly large simulation times. Therefore, consider minimizing the complexity of data being used in the model.