HDL Coder, Bus and Black Box
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I have a model I use with HDL coder, I have a Referenced Model in it called "AGC".
With the default options, the AGC model has it's code generated in a library called "work_agc" and all its files are mangled to start with the prefix "agc_". This doesn't work for me, so I generate the code for the AGC separately and refer to it as a black box in the parent model.
However, I now want to use Simulink Bus to tidy up the parent model, and I am not allowed to have a Bus comming out of a black box subsystem.
Is there a way I can have:
- The name I want for the AGC, i.e. library name agc and no prefix for the generated files. - Bus coming out of the toplevel.
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