Is it possible to have a simulink model and run a co simulation using the model along with verilog either user created or from the HDL Coder?

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I am looking to use the HDL Coder to create verilog from a simulink model but my question is, can this sumlink model be simulated along side the verilog?
I ask as I want to create the overall model of the system using Simulink and then code the system myself in verilog but I want to make sure the verilog I create matches what was expected from the Simulink model.
Thanks, Chris

Accepted Answer

Tim McBrayer
Tim McBrayer on 17 Nov 2016
Yes. The HDL Verifier tool allows cosimulation between Simulink and HDL code. This code can be generated by HDL Coder, or it can be handwritten code, or a combination of the two.
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Christopher Muir
Christopher Muir on 22 Nov 2016
Thanks for the help. I have looked over the HDL Verifier and completed the tutorials that Mathworks provide and I am now going to attempt to take a simple verilog block through HDL Verifier and co-sim it with a model from Simulink. Wish me luck!

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