Hi sir i am trying to convert matlab to vhdl but during test bench generation i am getting error like "error using divide",please guide to over come this error

## Begin Test Bench generation.
Error using divide (line 169)
Division by zero detected.
Early termination due to division by zero.

[Zeina Abdullah]

Hi, how did you solve this problem

Answer 1

[Andreas Goser]

As HDL Code generation is used in commerical projects and in-depth university projects, you likely have a license under software maintenance and I suggest you call into Technical Support for fundamental help.

Answer 2

[Tim McBrayer]

Please describe what you are doing when you see this message. Also, please provide as complete of an error log as you can, not just three words. If possible provide a simple set of reproduction steps, or at least a description of what you have tried to understand or work around this issue. As it stands I don't have any more to suggest than Andreas already suggested, because there is nothing to work with.