Simulink System Generator Query

how to generate a verilog code in simulink using system generator? I have generated the model for Image Negative using simulink. I am struggling to generate the verilog code. Help me with the steps. I need to generate the verilog code alone. I am not going to implement the design on FPGA kit. For your reference I am attaching the simulink model. I am getting the error while running the model. that error is displayed in the text file. For your reference I am attaching the same for your reference. Please specify the parameters for system generator block

Answer 1

[Tim McBrayer]

System Generator is a Xilinx product, not a MathWorks product. The error message states that you're hitting an internal error in SysGen and requests you contact Xilinx support, and also points you to the Xilinx Answers Database. Both of these seem to be good suggestions.