FIL Block Output Differs from Expected Value

[Summary]Hello,

I am using the HDL Coder Workflow Advisor to perform FPGA-in-the-Loop (FIL) verification. The workflow completes without errors and the FIL block is generated, but I'm having an issue where its output does not match the output of the original Simulink model (the expected value).

This problem is reproducible even with a very simple adder model. The attached Scope image shows a comparison of the outputs from that test. As you can see, there is a clear discrepancy between the expected value (dut_ref) and the FIL block's output.

Attached Image:

[Environment]

• MATLAB Version: R2025a
• HDL Coder Version: R2025a
• Target Tool: Xilinx Vivado 2024.2
• Target Device: Arty Z7-20

[Problem Details and Investigation]To investigate this issue, I generated a FIL block from a simple two-input adder model. The Synthesis & Implementation process in Vivado completes without errors, and the bitstream file is generated successfully. I have also confirmed that the generated wrapper HDL file correctly instantiates my adder design (the DUT).

However, when I run the FIL block in Simulink, the output is incorrect as shown in the image above. It appears that for some reason, the data transfer between Simulink and the physical FPGA is not occurring correctly.

[What I've Tried]

• I have lowered the target frequency to 25 Hz, and the problem still occurs, so I believe it is unlikely to be a timing issue.
• The same issue occurs after deleting the fil_prj folder and performing a clean rebuild.

[Questions]

1. In a situation like this, where synthesis and implementation complete without error, yet the FIL block's behavior differs from the expected value, what are the other possible causes?
2. Are there any other points to check or effective approaches to debug this problem?
3. Is this a known issue with specific tool versions?

Thank you for your time and assistance.

[Navya Seelam]

Hi,

Can you share the model? It will be helpful to look into the issue.

Also, one thing that you can check is if the HDL Cosimulation passes. This will validate the correctness of HDL code generated for the DUT. You can follow below example to generate the cosimulation model for Vivado and validate the HDL code generated.

https://www.mathworks.com/help/hdlcoder/ug/hdl-verifier-cosimulation-model-generation-in-hdl-coder.html

[Rito Sakima]

Thank you for your response.

The model I am currently working on is a simple adder that takes two inputs, adds them together, and outputs the result.

As for the cosimulation, I was able to run it successfully without any errors using the verification model generated during the HDL Coder Workflow Advisor process.

Answer 1

[Rito Sakima]

Dear all,

Please accept my sincere apologies for the delay in my response.

I am writing to inform you that the issue we discussed regarding the FIL block producing unexpected values has been successfully resolved.

Upon investigation, we determined that the root cause was that the bitstream was not being applied correctly. I misunderstood that the bitstream was automatically applied by simply executing the FIL block.

I would like to express my sincere gratitude to everyone who assisted in resolving this matter.

Answer 2

[Hiro Kawai]

I have tried FIL with the almost same condition.

• MATLAB Version: R2025a
• HDL Coder Version: R2025a
• Target Tool: Xilinx Vivado 2024.1
• Target Device: Arty S7 50

It seems the resuls is as expected. I can share the design, so please compare with yours?

[Rito Sakima]

Thank you for your response.

I regenerated the FIL block from the Simulink model you provided to make it compatible with the FPGA board I am using, but the same problem is still occurring.

Could this issue be because the FPGA board I am currently using is not an officially supported model?

[Rito Sakima]

This time, I created a simpler model that just passes the input directly to the output and generated a FIL block from it.

Using this model, I was able to get the expected results.

[Rito Sakima]

This time, I created a FIL block for a model that doubles the input. However, I'm encountering the same problem as before.

[Navya Seelam]

Hi Rito Sakima,

Which board did you choose to create FIL Project in HDL Coder Workflow Advisor? Since Arty Z7-20 is not supported by default, did you use FIL custom board workflow to create a board file for Arty Z7-20?