Is it feasible to implement a Stanley Controller in FPGA using Simulink and HDL Coder?

Hello, I am working on a project titled "Adaptive Headlamp Control using Stanley Controller" for autonomous vehicle navigation. The project consists of three objectives: (1) designing a Stanley Controller for lane prediction, which is completed and simulated in MATLAB Simulink; (2) modifying the controller to reduce prediction error and intelligently adjust the headlamp angle, which is currently in progress; and (3) implementing the finalized model on an FPGA using HDL Coder, which is the focus of this query. I am using MATLAB R2024b for this project. I would like to know if it is feasible to implement the Stanley Controller on an FPGA using Simulink and HDL Coder, and how to best handle components such as trigonometric functions (atan2, atan2d), floating-point to fixed-point conversions, and other HDL compatibility considerations. The current Simulink model computes the steering angle based on cross-track and heading error, and uses this value to calculate the headlamp angle as theta_headlamp = k * theta_steering. I plan to convert this model using HDL Workflow Advisor and deploy it on a Xilinx Artix-7 FPGA. Any advice on best practices, limitations, or recommended model structures for HDL conversion would be greatly appreciated.

Answer 1

[Vidhi Agarwal]

Hi @Eden,

• Feasibility of Stanley Controller on FPGA with HDL Coder: It is feasible, as the Stanley Controller's logic (cross-track error, heading error, steering calculation) can be mapped to hardware using Simulink and HDL Coder. Many similar vehicle guidance algorithms have been successfully ported to FPGAs for real-time, low-latency control.
• Handling Trigonometric Functions (atan2, atan2d): These blocks are mapped to CORDIC (COordinate Rotation DIgital Computer) algorithms in hardware, which are resource-efficient but have finite precision and latency. Best practices for this will include using Simulink blocks (Trigonometric Function set to atan2 or atan2d), not custom MATLAB code, for HDL compatibility, including pipelining the design if necessary, as CORDIC blocks introduce latency and simulate with fixed-point settings to evaluate accuracy and resource usage.
• Floating-Point to Fixed-Point Conversion: Use the Fixed-Point Tool in Simulink to propose and simulate fixed-point data types for your model. Quantize all signals and parameters, including gains and constants like your headlamp angle factor \( k \). Validate the fixed-point model against the floating-point reference to ensure accuracy, and choose word lengths—typically starting with 16 or 24 bits—to balance precision with FPGA resource usage.
• HDL Workflow Advisor & FPGA Deployment: To prepare your model for HDL code generation and FPGA deployment, first run the HDL Compatibility Checker in Simulink. Then, use the HDL Workflow Advisor to guide you through code generation, IP core integration, and deployment. Be sure to select your Artix-7 board as the target and use HDL Coder’s resource and timing estimation tools to verify that your design fits and meets performance requirements.

Be mindful that trigonometric functions (like CORDIC) and large word lengths can increase FPGA resource usage, so analyze and optimize your design accordingly. Avoid using dynamic memory, variable-size arrays, or unsupported blocks in MATLAB and Simulink. For debugging, take advantage of HDL Coder’s testbench generation and cosimulation features to thoroughly validate your design before deploying it to hardware.

Hope this helps!