Need help understanding how vector adressing on the HDL Ram Blocks for Burst Read and Write

I am trying to perform burst reads and writes with the True Dual Port RAM System block. The din_a is a [2x1] column vector. addr_a is a [2x1] column vector aswell.

My question is if I have say [4;5] as my din_a with the vector address [0;1] to addr_a. Does that store 4 in address 0 and 5 in address 1?

Because when I go back to read out the data, if my addr_a is [0;1], the output dout_a would just be [4;0] (5 is dropped), and what ever is stored in the second row is just the initial ram setting, in this case, 0.

For extra information my we_a is a [2x1] that is set 1 when writing and 0 when reading. my we_b doesn't go high during the initial writing phase so what wouldn't cause I problem I believe.

I just want clarification on how vector addressing works and there doesn't seem to be any information on vector ram addressing online. My goal is to burst read and write larger vectors simultaneously to each port in the dual port ram system but I want specific addressing for each word in the vector.

Please let me know if there are any resources I can look at or if there are any other solutions to this.

Thanks!

Here is an image of my set up. For instance I would want to store -0.5 in adress 3 and -0.1913... in adress 19. Please let me know if this is possible.

Answer 1

[Steven Hatcher]

There is a new feature for the RAM System blocks in R2025a to control vector access behavior. You can try it out with the R2025a prerelease. I believe it will satisfy your request for serial access on a single RAM. The serial access can also be performed at the clock rate when using Clock-Rate Pipelining. Otherwise, the RAM will be locally upsampled according to the vector size.

https://www.mathworks.com/help/releases/R2025a/hdlcoder/release-notes.html?startrelease=R2022a&endrelease=R2025a&rntext=vector+input+handling&groupby=release&sortby=descending&searchHighlight=vector+input+handling

Before R2025a, vector access with RAM blocks is always parallel. Multiple banks of RAMs will be inferred, which will multiply your total RAM consumption by the vector size and each element of the vector will have its own address space. This behavior is documented in the RAM block pages.

https://www.mathworks.com/help/hdlcoder/ref/truedualportramsystem.html?searchHighlight=%22vector+data%22&s_tid=srchtitle_support_results_6_%2522vector+data%2522