Hello,
I understand that you are encountering inaccessible inputs during MIL testing. This indicates that the Test Sequence block cannot access certain signals or parameters. There could be several reasons for this issue:
- If you designate a signal point as a test point, it prevents the signal from undergoing model optimizations such as Signal Storage Reuse. This renders the signal inaccessible and unobservable during simulation. For more information, refer to this documentation: https://www.mathworks.com/help/simulink/ug/working-with-test-points.html?searchHighlight=inaccessible&s_tid=srchtitle_support_results_1_inaccessible.
- Blocks that do not accept buses as input may implicitly convert a Virtual Bus to a Vector when received. When bus elements are treated as vectors, they become inaccessible. For more details, see this documentation:. https://www.mathworks.com/help/simulink/ug/bus-conversion.html?searchHighlight=inaccessible&s_tid=srchtitle_support_results_2_inaccessible.
- When a port element displays an inaccessible label, it indicates that the structure cannot access the output port value due to the model's structure and optimizations, such as Signal Storage Reuse, being applied to the model for generated code. For further information, refer to this documentation: https://www.mathworks.com/help/simulink/ug/displaying-block-outputs.html?searchHighlight=inaccessible&s_tid=srchtitle_support_results_3_inaccessible#mw_d6ff2be0-118a-45e0-9dc5-55f377ec97fa.
I hope that the information mentioned above helps you!
