Inconsistent SIL and Normal mode simulation results (Equivalence Criteria Failing )

Model setup is as below:

=> I have a model "Model_1" which is system under test for Normal and SIL level simulations.

Here i have attached the model snippet for better understanding

To test the model, I have created stub files (stub.c and stub.h) where I have defined functions to test the parameters of interest and the defined functions are called in test harness using C-callers ( Attached screenshots)

Using above method, MIL tests are passed without any Issues but at SIL level I am reading Values 0. Why am I getting this Error and how to fix this?

Answer 1

[Akshat Dalal]

The issue you are facing is an expected behavior of SIL simulation.

Consider a model that references a child model using the “Model Block” and we put the child model in SIL mode. The simulation semantics for this modelling pattern are as follows:

1. SIL simulation generates code only for the child model.
2. The generated code is built into an executable representing the child model.
3. The main model communicates with the child model’s executable.

Therefore, in the test-harness for your model, SIL simulation mode generates code for the “component under test” and runs that generated code as an executable that communicates with the test-harness.

However, the data space is not shared between the executable and the harness. Thus, any extern variable that the main-model writes to, and the test-harness reads from, are different.

In other words, global variables from the SIL model are not accessible from the harness.

A possible workaround for this issue is captured below:

You can enable global variables as function interfaces as outlined in the following documentation:

https://in.mathworks.com/help/simulink/gui/enable-custom-code-globals-as-function-interface.html

If this option is selected, the variables declared as global in the custom code can be used as global arguments on the block interface and they will appear as a port.

After enabling this feature, verifying that the C Caller blocks are modifying the global variables appropriately can be done in two ways:

1. Log the signal and do the verification after the simulation is done running.
2. Route that signal to the test-harness to do the verification.