Once the bitstream is generated using MATLAB's HDL Workflow Advisor, you primarily need the Xilinx Vivado Design Suite installed on the system, which includes all the necessary drivers to program the device. You can use the "Hardware Manager" or command-line tools to upload the bitstream to Vivado and deploy it on the device.
If your target FPGA is part of a "development board", you might need to download and install the corresponding "Board Supoprt Package" from the board vendor to access specific hardware features and I/O configurations within your MATLAB code.
Hope this helps you out!
