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About HDL Implementation of LTE OFDM Modulator and Detector Example

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Erdem Özyurt
Erdem Özyurt on 27 Mar 2015
Answered: Garrey Rice on 1 Apr 2015
With the R2015a a HDL optimized OFDM example comes. In the documents of the example it is said that, the output of the modulator has a BW between 1.4 MHz to 20 MHz. However when I connected a spectrum analyzer block to the output of the modulator block it gives just 1Hz. When I change the feed block with a bit generator block (with a sample rate like 1e-7) simulink gives error and says some of the blocks is fixed in minor step and for the others has sample time as 1. How can I use this example with the higher data rates to obtain higher BW and then download to FPGA? (I thought that changing the sample time one by one may cause timing problems also some blocks don't allow to change)

Answers (1)

Garrey Rice
Garrey Rice on 1 Apr 2015
Changing the bandwidth setting has the effect of changing the number of resource blocks in the LTE resource grid and consequently the number of subcarriers and IFFT points. However it does not change the sample time of the OFDM modulator in the Simulink model, which is why the Spectrum Analyzer does not show the correct frequency scaling by default.
You can change the sample rate setting of the Spectrum Analyzer so that it displays the correct frequency scaling without altering the sample time of the Simulink model. Click on View -> Spectum Settings (if the Spectrum Settings are not already displayed) and then change the Sample rate to the correct setting from the bandwidth table on the example help page. For example if you specify a bandwidth of 10 MHz then the corresponding sample rate would be 15.36 MHz. Alternatively you can set the Spectrum Analyzer Sample rate setting to
to pick up the sample rate automatically from the example parameters. Also, please note that the example automatically generates a correctly scaled spectrum plot once the simulation has completed.
Regarding FPGA implementation: in the example the Simulink sample time of the modulator is always set to 1. However on an FPGA this rate would correspond to one of the rates specified in the aforementioned bandwidth table. For example if you specify a bandwidth of 10 MHz then the modulator will use a 1024 point IFFT in the HDL implementation and you would need a 15.36 MHz sample rate on the FPGA.

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