Is there an option to generate HDL code with "Bus Data Read/Write with Strobe Synchronization"?

When generating HDL code for a DUT subsystem and an input port of the DUT is a vector, HDL Coder adds strobe registers so the elements of the vector read by the FPGA are synchronized (correspond to the same Processor time step). Same for vector ouput.

Here is a screenshot of the IP Core generation report for details:

Is there an option to generate these strobe registers for a DUT port that is a bus?

This would be useful when data consistency is needed but not of the same data type. As multirate bus are not allowed at DUT interface, a vector and a but are similar except the data type.

Coming back to the currently implemented feature (vector strobe registers), are there requirements that may prevent from generating strobe registers? Indeed, I have a model for which the strobe registers are not generated and I can't understand why.