HDL Coder Pipeline Sample Rate

I am using HDL Coder for controller implementation. My controller desired sample rate is far below that of the device it will run on. What is the cleanest way to insert pipeline registers havins sample rate of base device clock, as opposed to the controller base rate?

Thanks

Answer 1

[Girish Venkataramani]

Hi Jeff, very good question. What release of HDL Coder are you using?

This is a known issue and we are providing new capability in the latest release, 14b, which will come out in October this year. The new capability is called "Clock Rate Pipelining" and in this mode, the coder understands this sampling difference. When you then insert an input/output pipeline between your filter sections, it will insert it at the FPGA clock rate.

Unfortunately, for now with your current HDL Coder version, you will have to model your design at the FPGA clock rate to achieve the same behavior. I understand that this will slow down your simulation but it is the only way right now.

[Jeff]

I am using 2013a, and as you say am modelling design at FPGA clock rate. It is quite slow, but I appreciate the answer, and knowing that for the time being I handling it the right way.

Thanks

Answer 2

[Tim McBrayer]

HDL Coder has a diverse set of pipeline capabilities. It can add input and output pipelines, distribute delays automatically, enforce delays to be at a certain location, and more.

The simplest, and perhaps the most simplistic approach, is to add pipeline registers to the input and output ports via the right-click context menu of the top subsystem containing your design. (right-click > HDL Coder > HDL Block Properties). Then enable Distributed Pipelining, and HDL Coder will make a heuristic effort to distribute the pipeline registers efficiently throughout your design.

There are several other approaches, covering the full range from completely manual register insertion, to fully automatic as mentioned above. The documentation discusses the available capabilities and features.

[Jeff]

Hello Tim, I appreciate the reply. I am familiar with what you are describing. The difficulty comes when I would like to have my model running at 10KHz, and want to manually insert a pipeline between lets say two second order sections, and I want to have that pipeline be clock/enabled at my fpga clock rate, not 10KHz, because i dont want to add 10khz cycle latency.

I could simply do rate transitions, but the slow to fast transitions would a 10khz latency cycle unnecesserily.