Access DUT Registers on Intel Pure FPGA Board Using IP Core Generation Workflow
This example shows how to use the HDL Coder™ IP core generation workflow to develop reference designs for Intel® parts that do not use an embedded ARM® processor present but that still utilize the HDL Coder generated AXI interface to control the design under test (DUT). This example uses the HDL Verifier™ AXI Manager IP to access the HDL Coder generated DUT registers from MATLAB®. Alternatively, you can use the Intel Qsys JTAG to Avalon® Master Bridge IP to access the FPGA registers using Tcl commands in the Qsys system console. For the Intel JTAG AXI Master, you must create a custom reference design. The FPGA design is implemented on the Arrow® DECA MAX® 10 FPGA evaluation kit.
Intel Quartus® Prime Standard, with a supported version listed in HDL Language Support and Supported Third-Party Tools and Hardware
Arrow DECA MAX 10 FPGA evaluation kit
HDL Coder Support Package for Intel FPGA Boards
HDL Verifier Support Package for Intel FPGA Boards
HDL Coder Support Package for Intel SoC Devices (required only when you want to integrate the IP core into your own custom reference design)
Arrow DECA MAX 10 FPGA Evaluation Kit
This figure shows the Arrow DECA MAX 10 FPGA evaluation kit.
Example Reference Designs
Designs that can benefit from using the HDL Coder IP core generation workflow without using either an embedded ARM processor or an Embedded Coder™ support package but still leverage the HDL Coder generated AXI4 registers can include one of these IP sets.
HDL Verifier AXI Manager + HDL Coder IP Core
JTAG Master + HDL Coder IP Core
Nios® II + HDL Coder IP Core
PCIe® Endpoint + HDL Coder IP Core
This example includes two reference designs.
The Default System reference design uses MathWorks® IP and a MATLAB command line interface for issuing read and write commands. To use this design, you must have the HDL Verifier product.
The Intel JTAG to AXI Master reference design uses Quartus IP for the JTAG to AXI Master and requires using the Quartus Tcl console to issue read and write commands.
The two reference designs differ by only the JTAG manager IP that they use.
HDL Verifier AXI Manager Reference Design
In the IP core generation workflow of the HDL Workflow Advisor, in the Set Target Reference Design step, enable the Insert AXI Manager (HDL Verifier required) parameter. This option adds AXI Manager IP automatically into the reference design and connects the added IP to the DUT IP using the AXI4-slave interface. The next section details the steps to auto-insert the JTAG AXI Manager IP in the reference design.
Execute IP Core Workflow
Follow these steps to execute the IP core workflow for the Default System reference design, which uses JTAG AXI Manager IP. Using this reference design, you can generate an HDL IP core that blinks LEDs on the DECA board. To generate the HDL IP core, follow these steps.
1. Set up the Intel Quartus® tool path. Use your own Intel Quartus installation path by executing this command in MATLAB.
hdlsetuptoolpath('ToolName','Altera QUARTUS II', ... 'ToolPath','C:\intelFPGA\20.1\quartus\bin64\quartus.exe');
2. Open the Simulink model that implements LED blinking by executing this command in MATLAB.
3. Launch HDL Workflow Advisor from the
hdlcoder_led_blinking/led_counter subsystem by right-clicking the
led_counter subsystem and selecting HDL Code followed by HDL Workflow Advisor.
4. In step 1.1, set Target workflow to
IP Core Generation and Target platform to
Arrow DECA MAX 10 FPGA evaluation kit. Click Run This Task.
5. In step 1.2, set Reference design to
Default system. Under Reference design parameters, set Insert AXI Manager (HDL Verifier required) to
6. In step 1.3, set the interface of the Blink_frequency, Blink_direction, and Read_back ports to
AXI4. Set the interface of the LED port to
LEDs General Purpose [0:7].
7. Run the remaining steps in the workflow to generate a bitstream and program the target device.
Determine Addresses from IP Core Report
The base address for an HDL Coder IP core is defined as
0x00000000 for the Default System reference design, which uses the AXI Manager IP. You can see address setting in the generated IP core report as shown this figure.
The IP core report register address mapping table shows the offsets.
HDL Verifier Command Line Interface
If you have the HDL Verifier support package for Intel FPGA boards and select the AXI Manager reference design, then you can use the MATLAB command line interface to access the IP core that is generated by the HDL Coder product.
To write and read from the DDR memory, follow these steps.
1. Create an AXI manager object.
h = aximanager('Altera')
2. Issue a write commands. For example, disable the DUT.
3. Re-enable the DUT.
4. Read the current counter value.
5. Delete the object to free up the JTAG resource. If you do not delete the object, other JTAG operations, such as programming the FPGA, fail.
Intel JTAG to AXI Master Reference Design
Create a custom reference design to use the Intel JTAG to AXI Master IP in the reference design, and then add reference design files to the MATLAB path using the
Access the HDL Coder IP core registers using the Intel JTAG to AXI Master IP by using the base address that is defined in reference design plugin file.
Qsys System Console Tcl Commands for AXI Read and Write
Before opening a system console, choose the appropriate Qsys read and write commands. For this example, because all of the HDL Coder generated IP core registers are currently 32 bits, use these read and write commands.
% master_write_32 <service-path> <start-address> <list-of-32-bit-values> % master_read_32 <service-path> <start-address> <size-in-multiples-of-32-bits>
For example, write the 32 bit hex value 0x12345678 to the IP core register defined by offset 0x100 using a previously defined service path stored in the variable
% master_write_32 $jtag 0x100 0x12345678
Before you can generate reads and writes, you must first launch a system console and open a connection to the JTAG Master that issues the register reads and writes.
To open a connection to the JTAG Master, first set a variable that stores the service path (in this case, only one master exists).
% set jtag [lindex [get_service_paths master] 0]
Use the variable to open the JTAG Master in master mode.
% open_service master $jtag
Launch the Altera® system console and enter the commands to open the JTAG Master.
When you are done using the JTAG Master, close the connection by using this Tcl command.
close_service master $jtag
You can use the JTAG AXI Manager IP to interface with HDL Coder IP core registers in systems that do not have an embedded ARM processor, such as the MAX 10. You can use this IP as a first step to debug standalone HDL Coder IP cores, prior to hand coding software for soft processors, (such as Nios II), or as a way to tune parameters on a running system.