addMemoryInterface

Access memory regions on your FPGA or SoC hardware

Since R2023a

Syntax

addMemoryInterface(hFPGA)

addMemoryInterface(hFPGA,Name=Value)

Description

addMemoryInterface(hFPGA) adds a memory interface to the FPGA, hFPGA, that you can use to access regions of memory on your hardware by using MATLAB^®. Typically, these are regions of memory that are accessible by the AXI4 Master interface on your HDL Coder™ IP core. Accessing the same regions of memory from MATLAB allows you to exchange data with your IP core.

addMemoryInterface(hFPGA,Name=Value) adds a memory interface with one or more options specified as name-value arguments.

Examples

Add Memory Interface

Create a memory interface to read and write data from accessible memory regions.

Create an fpga object, hFPGA, for a Xilinx^® target.

hFPGA = fpga("Xilinx")

hFPGA = 

  fpga with properties:

       Vendor: "Xilinx"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]

    

Add the memory interface to the hFPGA object by using the addMemoryInterface function. Save the memory interface to hInterface.

hInterface = addMemoryInterface(hFPGA)

hInterface = 

  Memory with properties:

     InterfaceID: "Memory"
     BaseAddress: "0x0"
    AddressRange: "0x100000000"
     WriteDriver: [1×1 matlabshared.libiio.sharedmem.write]
      ReadDriver: [1×1 matlabshared.libiio.sharedmem.read]
      InputPorts: [0×0 string]
     OutputPorts: [0×0 string]

Add Memory Interface for a Specified Address Space

Use name-value arguments to create a memory interface at a specified address space.

Create a fpga object, hFPGA, for a Xilinx target.

hFPGA = fpga("Xilinx")

hFPGA = 

  fpga with properties:

       Vendor: "Xilinx"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]

    

Add the memory interface to the hFPGA object by using the addMemoryInterface function. Specify the memory interface name, base address and address range. Save the memory interface object to hInterface.

hInterface = addMemoryInterface(hFPGA, InterfaceID = "myInterface",...
BaseAddress = 0x80000000,AddressRange = 0x20000000)

hInterface = 

  Memory with properties:

     InterfaceID: "myInterface"
     BaseAddress: "0x80000000"
    AddressRange: "0x20000000"
     WriteDriver: [1×1 matlabshared.libiio.sharedmem.write]
      ReadDriver: [1×1 matlabshared.libiio.sharedmem.read]
      InputPorts: [0×0 string]
     OutputPorts: [0×0 string]

Input Arguments

hFPGA — Target FPGA object

fpga object

Target FPGA object, specified as an fpga object.

Name-Value Arguments

Specify optional pairs of arguments as Name1=Value1,...,NameN=ValueN, where Name is the argument name and Value is the corresponding value. Name-value arguments must appear after other arguments, but the order of the pairs does not matter.

Before R2021a, use commas to separate each name and value, and enclose Name in quotes.

Example: hInterface = addMemoryInterface(hFPGA,InterfaceID = "myInterface") creates a memory interface object with InterfaceID as myInterface.

InterfaceID — Name of memory interface

"Memory" | string

Name of memory interface, specified as a string.

BaseAddress — Base address

0x0 (default) | numeric value

Base address of the memory interface, specified as a numeric value.

Example: 0x40010000

AddressRange — Address range

numeric value

Address range for the memory interface, specified as a numeric value.

Example: 0x10000

WriteDeviceName — Name and path of IIO device

"mwipcore0:sharedmem0:wr0" (default) | string array

Name and path of the IIO device to write to, specified as a string array. When you generate an IP core using the HDL Workflow Advisor, the default name is mwipcore0:sharedmem0:wr0.

Example: "mwipcore0:sharedmem0:wr0"

ReadDeviceName — Name and path of IIO device

"mwipcore0:sharedmem0:rd0" (default) | string array

Name and path of the IIO device to read from, specified as a string array. When you generate an IP core using the HDL Workflow Advisor, the default name is mwipcore0:sharedmem0:rd0.

Example: mwipcore0:sharedmem0:rd0

WriteDriver — AXI driver to perform memory write operation

driver object

Name of the AXI driver that you use to write data into. You can specify this property as the HDL Verifier™ aximanager object for standalone FPGA boards. For SoC platforms, HDL Coder creates the drivers automatically.

Example: "aximanager('Xilinx')"

ReadDriver — AXI driver to perform memory read operation

driver objectobject

Name of the AXI driver that you use to read data from. You can specify this property as the HDL Verifier aximanager object for standalone FPGA boards that do not have an embedded ARM^® processor. For SoC platforms, HDL Coder creates the drivers automatically.

Example: "aximanager('Xilinx')"

AddressWidth — Address width of memory region accessed by memory interface

32 (default) | 64

Address width of the memory region that is accessed by this memory interface, specified as either 32 bits or 64 bits.

Example: AddressWidth=32

Version History

Introduced in R2023a