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hdlcoder.DUTPort

DUT port from an HDL Coder generated IP core, saved as an object array

Description

This object represents each DUT port name from an HDL Coder™ generated IP core. The object represents the ports of your DUT on the target hardware. When you generate an HDL IP core by running the IP Core Generation workflow, you map the ports to AXI4 slave or AXI4-Stream interfaces. The port object contains information about these DUT ports and the interfaces it is mapped to, based on the interface mapping information in the Target platform interface table of the Set Target Interface task. After you use the mapPort function, you can write to or read from the DUT ports by using the writePort and .readPort functions.

Creation

Description

example

hPort = hdlcoder.DUTPort(Name) creates a DUT port object as an object array, with additional properties specified by name-value pair arguments.

Properties

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Name of the input or output port of the DUT subsystem in your original model. When you run the IP Core Generation workflow, you obtain this information from the Port Name section of the Target platform interface table.

Example: hPort = hdlcoder.DUTPort("h_in", ...)

Data Types: string | char

Direction of the DUT port, specified as IN or OUT.

Example: hPort = hdlcoder.DUTPort(..., "Direction", "OUT", ...)

Data Types: char

Data type of the DUT port that is mapped to the AXI interface, specified as a MATLAB® numeric type such as uint32 or a numerictype object. When you run the IP Core Generation workflow, you obtain this information from the Data Type section of the Target platform interface table.

Example: hPort = hdlcoder.DUTPort(..., "DataType", numerictype(1,16,10), ... )

Data Types: uint8 | uint16 | uint32 | uint64

Dimensions of the DUT port that is mapped to the AXI interface, specified as an integer array or any other data type. The dimensions depend on whether the port mapped is a scalar or vector. For a scalar port, the Dimension is [1 1], and for an N-dimensional vector port, it is [1 N]. When you run the IP Core Generation workflow, you obtain this information from the Data Type section of the Target platform interface table.

Example: hPort = hdlcoder.DUTPort(..., "Dimension", [1 6], ...)

Data Types: int8 | int16 | int32 | int64 | single | double

Target platform interface that the DUT port is mapped to, specified as a string or character array. When you run the IP Core Generation workflow, you obtain this information from the Target Platform Interfaces section of the Target platform interface table.

Example: hPort = hdlcoder.DUTPort(..., "IOInterface", "AXI4-Lite")

Data Types: string | char

Target platform interface mapping information, specified as a character array, string array, or numeric type.

Example: hPort = hdlcoder.DUTPort(..., "IOInterfaceMapping", "0x100")

Data Types: string | char

Examples

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Create an fpga object to connect to a target device and then use hdlcoder.DUTPort object to specify the DUT port.

Create an fpga object for the target device.

hFPGA = fpga("Xilinx")
hFPGA = 

  fpga with properties:

       Vendor: "Xilinx"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]
    

Add the AXI4 slave interface to the hFPGA object by using the addAXI4SlaveInterface function.

%% AXI4-Lite
addAXI4SlaveInterface(hFPGA, ...
	"InterfaceID", "AXI4-Lite", ...
	"BaseAddress", 0xA0000000, ...
	"AddressRange", 0x10000);

Create a hdlcoder.DUTPort object for the AXI4-Lite Interface. After you create the object, you can map the port to the IO interface by using the mapPort function.

% ...
hPort_h_in1 = hdlcoder.DUTPort("h_in1", ...
	"Direction", "IN", ...
	"DataType", numerictype(1,16,10), ...
	"Dimension", [1 1], ...
	"IOInterface", "AXI4-Lite", ...
	"IOInterfaceMapping", "0x100");

mapPort(hFPGA, hPort_h_in1);

 
hPort_h_in1 = 

  DUTPort with properties:

                  Name: "h_in1"
             Direction: IN
              DataType: [1×1 embedded.numerictype]
             Dimension: [1 1]
           IOInterface: "AXI4-Lite"
    IOInterfaceMapping: "0x100"

Create an fpga object to connect to a target device and then use hdlcoder.DUTPort object to specify the DUT port.

Create an fpga object.

hFPGA = fpga("Xilinx")
hFPGA = 

  fpga with properties:

       Vendor: "Xilinx"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]
    

Add the AXI4-Stream interface to the hFPGA object by using the addAXI4StreamInterface function.

%% AXI4-Stream
addAXI4StreamInterface(hFPGA, ...
	"InterfaceID", "AXI4-Stream", ...
	"WriteEnable", true, ...
       "ReadEnable", true, ...
	"WriteFrameLength", 1024, ...
	"ReadFrameLength", 1024);

Create a hdlcoder.DUTPort object for an AXI4-Stream Interface. After you create the object, you can map the port to the IO interface by using the mapPort function.

hPort_x_in_data = hdlcoder.DUTPort("x_in_data", ...
	"Direction", "IN", ...
	"DataType", numerictype(1,16,10), ...
	"Dimension", [1 1], ...
	"IOInterface", "AXI4-Stream")

hPort_y_out_data = hdlcoder.DUTPort("y_out_data", ...
	"Direction", "OUT", ...
	"DataType", numerictype(1,32,20), ...
	"Dimension", [1 1], ...
	"IOInterface", "AXI4-Stream")

mapPort(hFPGA, [hPort_x_in_data, hPort_y_out_data]);
 hPort_x_in_data = 

  DUTPort with properties:

                  Name: "x_in_data"
             Direction: IN
              DataType: [1×1 embedded.numerictype]
             Dimension: [1 1]
           IOInterface: "AXI4-Stream"
    IOInterfaceMapping: ""

hPort_y_out_data = 

  DUTPort with properties:

                  Name: "y_out_data"
             Direction: OUT
              DataType: [1×1 embedded.numerictype]
             Dimension: [1 1]
           IOInterface: "AXI4-Stream"
    IOInterfaceMapping: ""

Introduced in R2020b