Hierarchical Designs and Synchronous Hardware Behavior
R2026bTo model large designs, you can divide your model into subsystems and create hierarchical designs. For synchronous hardware behavior and to generate hardware-friendly HDL code, use the State Control block inside the subsystems.
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Model Settings
| Code reuse | Specify whether to generate a reusable file for subsystems (Since R2022a) |
| Generate parameterized HDL code from masked subsystem | Generate reusable HDL code for subsystems |
| Use “rising_edge/falling_edge” style for registers | Use rising_edge or falling_edge to detect
clock transitions in generated code |
| Atomic subsystems | Share Atomic Subsystem blocks with resource sharing optimization |
Blocks
 | Unit Delay Enabled Synchronous | Delay input signal by one sample period when external Enable signal is true |
 | Unit Delay Resettable Synchronous | Delay input signal by one sample period when external Reset signal is false |
 | Unit Delay Enabled Resettable Synchronous | Delay input signal by one sample period when external Enable signal is true and external Reset signal is false |
 | Tapped Delay Enabled Synchronous | Delay scalar signal multiple sample periods and output all delayed versions when external Enable signal is true (Since R2023a) |
 | Tapped Delay Resettable Synchronous | Delay scalar signal multiple sample periods and output all delayed versions when external Reset signal is false (Since R2023a) |
 | Tapped Delay Enabled Resettable Synchronous | Delay scalar signal multiple sample periods and output all delayed versions when external Enable signal is true and external Reset signal is false (Since R2023a) |
 | Enabled Delay | Delay input signal by fixed or variable sample periods when external enable signal is true (Since R2024b) |
 | Enabled Resettable Delay | Delay input signal by fixed or variable sample periods when external Enable signal is true and external Reset signal is false (Since R2024b) |
 | State Control | Specify synchronous reset and enable behavior for blocks with state |
 | Synchronous Subsystem | Represent subsystem that has synchronous reset and enable behavior |
 | Enabled Synchronous Subsystem | Represent enabled subsystem that has synchronous reset and enable behavior |
 | Resettable Synchronous Subsystem | Represent resettable subsystem that has synchronous reset and enable behavior |
Topics
- Synchronous Subsystem Behavior with the State Control Block
Description of a State Control Block and how it generates cleaner HDL code.
- Generating HDL Code for Subsystems with Array of Buses
Generate HDL code for subsystems that use array of buses in the design.
- Generate Reusable Code for Subsystems
Generate shared code for identical subsystems or subsystems identical except for their mask parameter values.
- Generate HDL Code for Blocks Inside For Each Subsystem
An example that shows how to model and generate HDL code for blocks inside a For Each Subsystem.
- Generate HDL Code with Record or Structure Types for Bus Signals
Generate VHDL® code with record or structure types for bus signals at different subsystem-level interfaces.
Featured Examples
Using the State Control Block to Generate More Efficient Code with HDL Coder
Use the State Control block to generate hardware-friendly HDL code using HDL Coder™.
Resettable Subsystem Support in HDL Coder
Use Resettable Subsystems in HDL Coder™.
Generate HDL Code from For Each Subsystem Blocks
How a For Each Subsystem block implements a cascaded CORDIC (Coordinate Rotation Digital Computer) square root pipeline with a parameterized number of cores. In this example, you examine the model architecture, verify numerical accuracy against a reference function, and generate HDL code by using HDL Coder™.
