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Tool Setup

Synthesis Tool Path Setup

hdlsetuptoolpath Function

To use HDL Coder™ with one of the supported third-party FPGA synthesis tools, add the tool to your system path using the hdlsetuptoolpath function. Add the tool to your system path before opening the HDL Workflow Advisor. If you already have the HDL Workflow Advisor open, see Add Synthesis Tool for Current HDL Workflow Advisor Session.

Add Synthesis Tool for Current HDL Workflow Advisor Session

Simulink to HDL Workflow

  1. At the MATLAB® command line, use the hdlsetuptoolpath function to add the synthesis tool.

  2. In the HDL Workflow Advisor, in the Set Target > Set Target Device and Synthesis Tool step, to the right of Synthesis tool, click Refresh.

    The synthesis tool is now available.

MATLAB to HDL Workflow

  1. At the MATLAB command line, use the hdlsetuptoolpath function to add the synthesis tool.

  2. In the HDL Workflow Advisor, in the Select Code Generation Target step, to the right of Synthesis tool, click Refresh list.

    The synthesis tool is now available.

Check Your Synthesis Tool Setup

To check your Intel® Quartus Prime Standard synthesis tool setup in MATLAB, try launching the tool with the following command:

!quartus

To check your Intel Quartus Pro synthesis tool setup in MATLAB, try launching the tool with the following command:

!qpro

To check your Xilinx® Vivado® synthesis tool setup in MATLAB, try launching the tool with the following command:

!vivado

To check your Xilinx ISE synthesis tool setup in MATLAB, try launching the tool with the following command:

!ise

To check your Microsemi® Libero® SoC synthesis tool setup in MATLAB, try launching the tool with the following command:

!libero

Supported Tool Versions

For supported tool versions, see Third-Party Synthesis Tools and Version Support.

HDL Simulator Setup

To open the HDL simulator from MATLAB, enter these commands:

MATLAB Command to Open HDL Simulator

HDL SimulatorCommand to Open the Simulator
Cadence Incisive® nclaunch (HDL Verifier)
Mentor Graphics® ModelSim® vsim (HDL Verifier)

For example, to open the Mentor Graphics ModelSim simulator, enter this command:

vsim('vsimdir','C:\Program Files\ModelSim\questasim\10.5c\win64\vsim.exe')

To learn more about how to set up ModelSim, Questa®, or Incisive® for HDL simulation, or for cosimulation with HDL Verifier™, see HDL Simulator Startup (HDL Verifier).

Add Simulation Tool for Current HDL Workflow Advisor Session

MATLAB to HDL Workflow

  1. Set up your simulation tool.

  2. In the HDL Workflow Advisor, in the HDL Verification > Verify with HDL Test Bench task, click Refresh list.

    The simulation tool is now available.

Xilinx System Generator Setup for ModelSim Simulation

To generate ModelSim simulation scripts for a design containing Xilinx System Generator blocks, you must:

  • Have compiled Xilinx simulation libraries.

  • Specify the path to your compiled libraries.

Required Libraries for Vivado and ISE

To generate ModelSim simulation scripts, you must have the following compiled Xilinx simulation libraries for your EDA simulator and target language:

  • unisim

  • simprim

  • xilinxcorelib

To learn how to compile these libraries, refer to the Xilinx documentation.

  • For Vivado, see compile_simlib.

  • For ISE, see compxlib.

Specify Path to Required Libraries

Specify the path to your compiled Xilinx simulation libraries by setting the XilinxSimulatorLibPath parameter for your model.

For example, you can use hdlset_param to set XilinxSimulatorLibPath:

libpath = '/apps/Xilinx_ISE/XilinxISE-13.4/Linux/ISE_DS/ISE/vhdl/
   mti_se/6.6a/lin64/xilinxcorelib';
hdlset_param (bdroot, 'XilinxSimulatorLibPath', libpath);

Altera DSP Builder Setup

To generate code for a design containing both Altera® DSP Builder and Simulink® blocks, you must open MATLAB with Altera DSP Builder. For details, refer to the Altera DSP Builder documentation.

FPGA Simulation Library Setup

To map your design to an Altera or a Xilinx FPGA simulator library:

  • Use Xilinx LogiCORE® IP Floating-Point Operator v5.0 or Altera floating-point megafunction IP cores.

  • Specify the compiled simulation library and the target language for your EDA simulator. Use XilinxCoreLib simulation library for Xilinx LogiCORE IP and the EDA simulation library compiler for Altera megafunction IP.

    To learn how to compile this library, refer to the Xilinx compxlib documentation .

  • Specify the path to your compiled Altera or Xilinx simulation libraries. Altera provides the simulation model files in \quartus\eda\sim_lib folder. Set the SimulationLibPath parameter for your DUT.

    For example, you can use hdlset_param to set SimulationLibPath:

    myDUT = gcb;
    libpath = '/apps/Xilinx_ISE/XilinxISE-13.4/Linux/ISE_DS/ISE/vhdl/
       mti_se/6.6a/lin64/xilinxcorelib';
    hdlset_param (myDUT, 'SimulationLibPath', libpath);

    You can also specify the simulation library path from the HDL Code Generation > Test Bench pane in the Configuration Parameters dialog box.

C/C++ Compiler Setup

HDL Coder locates and uses a supported installed compiler. For most platforms, a default compiler is supplied with MATLAB. For a list of supported compilers, see Supported Compilers.

See Also

Related Topics