Basic HDL Code Generation Workflow

You can use HDL Coder™ to generate synthesizable VHDL^®, Verilog^®, and SystemVerilog code from a Simulink^® model or MATLAB^® algorithm. You can use the generated HDL code for FPGA programming, ASIC prototyping, and production design. Using HDL Workflow Advisor, you can deploy the generated HDL code on Xilinx^®, Intel^®, and Microchip boards. You can optimize your design for speed and area, highlight critical paths, and generate resource usage estimates before synthesis.

Develop MATLAB or Simulink Design

You can develop a design for HDL code generation in MATLAB and Simulink. You can generate code from your Simulink model or MATLAB algorithm by using HDL Coder. Write the MATLAB algorithm with syntax and functions that are compatible with HDL code generation. Use HDL-compatible Simulink blocks for creating your design with Simulink. To learn more, see Create HDL-Compatible Simulink Model.

Set Up HDL Coder Project

To generate HDL code from your MATLAB algorithm, create and set up the HDL Coder project for your MATLAB design. Add the MATLAB files to the HDL Coder project for which you want to generate HDL Code. To learn more, see Create and Set Up Your Project.

Check HDL Compatibility with HDL Code Advisor

You can check the HDL compatibility of your Simulink model by using HDL Code Advisor. The HDL Code Advisor tool verifies and updates your Simulink model or subsystem for compatibility with HDL code generation. The Model Checker tool checks for model configuration settings, ports and subsystem settings, block settings, support for native floating point, and conformance to the industry-standard rules. For more information, see Check HDL Compatibility of Simulink Model Using HDL Code Advisor.

Generate HDL Code

After you design your HDL-compatible Simulink model or MATLAB algorithm, you can generate the HDL code using HDL Coder. You can select the desired target language, such as VHDL, Verilog, or SystemVerilog. HDL Coder compiles the model before generating code. HDL Coder displays progress messages in the MATLAB Command Window with links to the configuration set and the generated HDL files.

See Also

• Generate HDL Code from Simulink Model

• Basic HDL Code Generation and FPGA Synthesis from MATLAB

Verify Generated HDL Code

After you generate the HDL code, you can test and verify your design using HDL test bench for your Simulink model or MATLAB algorithm. A test bench includes stimulus data generated by signal sources, component instantiation, and clock, reset, and clock enable inputs to drive the entity under test.

During a test bench run, the software compares the generated output data to the outputs of the HDL model for verification. You can simulate the generated test bench and script files by using the Siemens^® ModelSim™ simulator. To learn more, see Verify Generated HDL Code.

Deploy Generated Code to Target Hardware

HDL Coder includes a workflow advisor. This tool automates prototyping generated code on Xilinx, Intel, and Microchip boards and generates IP cores for ASIC and FPGA workflows. Using HDL Coder, you can deploy your MATLAB or Simulink design:

• On standalone FPGA boards, such as an Intel FPGA or a Xilinx FPGA board.

• On platforms that have a separate FPGA and processor, such as the Simulink Real-Time target machine with FPGA I/O boards.

• As hardware and software on system-on-chip (SoC) platforms, such as Xilinx Zynq^®, Intel SoC, or Microchip SoC.

See Also

• Get Started with IP Core Generation from Simulink Model

• Get Started with IP Core Generation for Intel SoC Devices

• Get Started with IP Core Generation for Microchip PolarFire SoC Devices

Optimize Design for Speed and Area

You can use the speed and area optimization methods to meet design requirements such as resource usage, critical path estimation, and timing requirements. Apply optimizations to generate more hardware-efficient HDL code. Use area and speed optimizations in HDL Coder to save resources and improve the timing of your design on the target FPGA device. The optimizations do not change the functional behavior of your algorithm.

You can initially generate HDL code and synthesize your design on your FPGA platform without enabling optimizations. If the design does not meet the timing requirements, you can enable optimizations and rerun the workflow until your design meets the area and speed requirements. To learn more about types of optimization, see Speed and Area Optimizations in HDL Coder.