Basic HDL Algorithms
The HDL Coder block library contains many basic blocks that you can add to your Simulink modeling environment and develop your HDL algorithm. These blocks include input sources, output sinks, and blocks that perform basic to complex math and trigonometric operations.
To filter the Simulink Library Browser to show only HDL-supported blocks, enter
hdllib. The blocks listed in this section
include those blocks that are only available in the
HDL Coder library. Blocks such as Add and
Product are available in the Simulink library in the
For a filtered list of Simulink blocks supported for HDL code generation, see Simulink Block List (HDL Code Generation).
|Display blocks that are compatible with HDL code generation|
Test Points and Diagnostics
Logic and Bit Operations
|Bit Concat||Concatenates up to 128 input words into single output|
|Bit Reduce||AND, OR, or XOR bit reduction on all input signal bits to single bit|
|Bit Rotate||Rotate input signal by bit positions|
|Bit Shift||Logical or arithmetic shift of input signal|
|Bit Slice||Return field of consecutive bits from input signal|
|Bits to Word||Convert vector of bits to integer (Since R2023a)|
|Word to Bits||Converts real numbers to vector of bits (Since R2023a)|
HDL Math Library
|Atan2||Implement control signal based |
|Sin||Implement control signal based sine function (Since R2020b)|
|Cos||Implement control signal based cosine function (Since R2020b)|
|Cos+jSin||Implement control signal based |
|SinCos||Implement control signal based sine and cosine function (Since R2020b)|
|rSqrt||Implement control-signal-based reciprocal square root function (Since R2020b)|
|Sqrt||Implement control-signal-based square root function (Since R2020b)|
|Divide||Implement control-signal-based division operation (Since R2020b)|
|Reciprocal||Implement control-signal-based reciprocal operation (Since R2020b)|
- Model and Debug Test Point Signals with HDL Coder
An example that shows how to add test points to signals in your model and debug these signals in the generated HDL code.
- Generate DUT Ports for Tunable Parameters
Generate DUT ports for tunable parameters.
- Generate Code with Annotations or Comments
How to add annotations to generated HDL code using the DocBlock and model annotations.
- Scalarization of Vector Ports in Generated VHDL Code
Flatten vector signals on entire model or at DUT level into a structure of scalar signals in generated VHDL or SystemVerilog code.
- Simulate and Generate HDL Code for the Float Typecast Block
Use Float Typecast block to cast input to floating-point or fixed-point.