Bit Slice
Return field of consecutive bits from input signal
- Library:
HDL Coder / Logic and Bit Operations

Description
The Bit Slice block returns a field of consecutive bits from the input
signal. Specify the lower and upper boundaries of the bit field by using zero-based indices in
the LSB Position and MSB Position parameters. For an
input word size WS
, LSB Position and MSB
Position must satisfy these constraints:
WS > MSB Position >= LSB Position >= 0
Ports
Input
Port_1
— Input Signal
scalar | vector
Input signal on which the bit-rotation is performed. The input signal has a maximum bit width of 128.
Data Types: int8
| int16
| int32
| int64
| uint8
| uint16
| uint32
| uint64
| Boolean
| fixed point
Output
Port_1
— Output Signal
scalar | vector
Output signal that is bit-sliced. The word length of the output is computed as
(MSB Position - LSB Position) + 1
, where MSB
Position and LSB Position are block
parameters.
Data Types: uint8
| uint16
| uint32
| uint64
| fixed point
Parameters
MSB Position
— Most significant bit position
7 (default)
Specifies the bit position (zero-based) of the most significant bit (MSB) of the field to extract.
For an input word size WS
,MSB Position must
satisfy these constraints:
WS > MSB Position >= LSB Position >= 0
Programmatic Use
Block parameter:
lidk |
Type: string scalar | character vector |
Value: positive integer value such that satisfies the constraints mentioned previously |
Default:
'7' |
LSB Position
— Least significant bit position
0 (default)
Specifies the bit position (zero-based) of the least significant bit (LSB) of the field to extract.
For an input word size WS
, LSB Position must
satisfy these constraints:
WS > MSB Position >= LSB Position >= 0
Programmatic Use
Block parameter:
ridk |
Type: string scalar | character vector |
Value: positive integer value such that satisfies the constraints mentioned previously |
Default:
'0' |
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
This block has a single, default HDL architecture.
General | |
---|---|
ConstrainedOutputPipeline | Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is
|
InputPipeline | Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
OutputPipeline | Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
Version History
See Also
Blocks
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