Complex Burst Qless QR Decomposition
Qless QR decomposition for complexvalued matrices
 Library:
FixedPoint Designer HDL Support / Matrices and Linear Algebra / Matrix Factorizations
Description
The Complex Burst Qless QR Decomposition block uses QR decomposition to compute the economy size uppertriangular R factor of the QR decomposition A = QR, where A is a complexvalued matrix, without computing Q. The solution to A'Ax = B is x = R\R'\b.
Ports
Input
A(i,:)
— Rows of complex matrix A
vector
Rows of complex matrix A
, specified as a vector.
A is a mbyn matrix where m ≥ 2 and n ≥ 2. If A is a fixedpoint data type,
A must be signed and use binarypoint scaling. Slopebias
representation is not supported for fixedpoint data types.
Data Types: single
 double
 fixed point
Complex Number Support: Yes
validIn
— Whether inputs are valid
Boolean
scalar
Whether inputs are valid, specified as a Boolean scalar. This control signal
indicates when the data at the A(i,:) input port is valid. When
this value is 1 (true
) and the value at ready
is 1 (true
), the block captures the values at the
A(i,:) input port. When this value is 0
(false
), the block ignores the input samples.
After sending a true
validIn signal, there may be some delay before
ready is set to false
. To ensure all data is
processed, you must wait until ready is set to
false
before sending another true
validIn signal.
Data Types: Boolean
restart
— Whether to clear internal states
Boolean
scalar
Whether to clear internal states, specified as a Boolean scalar. When this value
is 1 (true
), the block stops the current calculation and clears all
internal states. When this value is 0 (false
) and the
validIn value is 1 (true
), the block begins
a new subframe.
Data Types: Boolean
Output
R(i,:)
— Rows of uppertriangular matrix R
scalar  vector
Rows of the economy size QR decomposition matrix R, returned as a scalar or vector. R is an uppertriangular matrix. The output at R(i,:) has the same data type as the input at A(i,:).
Data Types: single
 double
 fixed point
validOut
— Whether output data is valid
Boolean
scalar
Whether the output data is valid, specified as a Boolean scalar. This control
signal indicates when the data at output port R(i,:) is valid.
When this value is 1 (true
), the block has successfully computed
the matrix R. When this value is 0 (false
), the
output data is not valid.
Data Types: Boolean
ready
— Whether block is ready
Boolean
scalar
Whether the block is ready, returned as a Boolean scalar. This control signal
indicates when the block is ready for new input data. When this value is
1
(true
) and the validIn
value is 1
(true
), the block accepts input data
in the next time step. When this value is 0
(false
), the block ignores input data in the next time
step.
After sending a true
validIn signal, there may be some delay before
ready is set to false
. To ensure all data is
processed, you must wait until ready is set to
false
before sending another true
validIn signal.
Data Types: Boolean
Parameters
Number of rows in matrix A
— Number of rows in matrix A
4
(default)  positive integervalued scalar
Number of rows in input matrix A, specified as a positive integervalued scalar.
Programmatic Use
Block Parameter:
m 
Type: character vector 
Values: positive integervalued scalar 
Default:
4 
Number of columns in matrix A
— Number of columns in matrix A
4
(default)  positive integervalued scalar
Number of columns in input matrix A, specified as a positive integervalued scalar.
Programmatic Use
Block Parameter:
n 
Type: character vector 
Values: positive integervalued scalar 
Default:
4 
Model Examples
Tips
Use fixed.getQlessQRDecompositionModel(A)
to generate a template model
containing a Complex Burst Qless QR Decomposition block for complexvalued
input matrix A
.
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
Slopebias representation is not supported for fixedpoint data types.
HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
This block has a single, default HDL architecture.
General  

ConstrainedOutputPipeline  Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is

InputPipeline  Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

OutputPipeline  Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

Supports fixedpoint data types only.
FixedPoint Conversion
Design and simulate fixedpoint systems using FixedPoint Designer™.
A must be signed and use binarypoint scaling. Slopebias representation is not supported for fixedpoint data types.
See Also
Blocks
 Real Burst Qless QR Decomposition  Complex PartialSystolic Qless QR Decomposition  Complex Burst QR Decomposition
Functions
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