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Deep Learning Processor IP Core Report

When you generate a deep learning processor IP core, Deep Learning HDL Toolbox™ generates an HTML custom IP core report. The report describes the behavior and content of the generated custom IP core. During custom processor generation, AXI4 slave registers are created to enable MATLAB® or other master devices to control and program the deep learning (DL) processor IP core.

The DL processor IP core is generated by using the HDL Coder™ IP core generation workflow. The generated IP core contains a standard set of registers. For more information, see Custom IP Core Generation (HDL Coder).

For the full list of register offsets, see the Register Address Mapping table in the generated deep learning (DL) processor IP core report.

Summary

This section shows the Deep Learning HDL Toolbox settings when you generated the custom IP core. This image is an example of the information in the summary section.

IP core report summary section

Target Interface Configuration

This section shows how your model design under test (DUT) ports map to the target hardware interface and the processor/FPGA synchronization mode. This image is an example of the information in the target interface configuration section:

Sample target interface configuration section of generic deep learning processor IP core report

Register Address Mapping

During custom processor generation, AXI4 slave registers are created to enable MATLAB or other master devices to control and program the deep learning (DL) processor IP core.

The deep learning processor IP core is generated by using the HDL Coder IP core generation workflow. The generated IP core contains a standard set of registers. For more information, see Custom IP Core Generation (HDL Coder). This image shows you a sample of the generated register address mapping table:

IP Core User Guide

This section gives a high-level overview of the generated IP core architecture and instructions to integrate the IP core into your reference design. This image shows a sample of the information available in the user guide section:

IP Core File List

This section lists the files and folders that are a part of the generated deep learning processor IP core. This image shows an example of the list of generated files:

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