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optimizeConfigurationForNetwork

Class: dlhdl.ProcessorConfig
Package: dlhdl

Retrieve optimized network-specific deep learning processor configuration

Syntax

optimizeConfigurationForNetwork(processorConfigObject,network)

Description

optimizeConfigurationForNetwork(processorConfigObject,network) returns an optimized deep learning processor configuration for the object specified by the network argument.

Input Arguments

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Instance of the processor configuration object, specified as a dlhdl.ProcessorConfig object.

Name of network object for optimized deep learning processor configuration, specified as a SeriesNetwork, DAGNetwork, yolov2ObjectDetector, or dlquantizer object.

Example: optimizeConfigurationForNetwork(snet)

Examples

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  1. Create a dlhdl.ProcessorConfig object.

    net = mobilenetv2;
    hPC = dlhdl.ProcessorConfig;
  2. To retrieve an optimized processor configuration, call the optimizeConfigurationForNetwork method.

    hPC.optimizeConfigurationForNetwork(net)
    ### Optimizing processor configuration for deep learning network begin.
    ### Optimizing series network: Fused 'nnet.cnn.layer.BatchNormalizationLayer' into 'nnet.cnn.layer.Convolution2DLayer'
    ### Note: Processing module "conv" property "InputMemorySize" changed from "[227 227 3]" to "[224 224 3]".
    ### Note: Processing module "conv" property "OutputMemorySize" changed from "[227 227 3]" to "[112 112 32]".
    ### Note: Processing module "conv" property "FeatureSizeLimit" changed from "2048" to "1280".
    ### Note: Processing module "conv" property "LRNBlockGeneration" changed from "on" to "off" because there is no LRN layer in the deep learning network.
    ### Note: Processing module "fc" property "InputMemorySize" changed from "25088" to "1280".
    ### Note: Processing module "fc" property "OutputMemorySize" changed from "4096" to "1000".
    
                        Processing Module "conv"
                                ModuleGeneration: 'on'
                              LRNBlockGeneration: 'off'
                                ConvThreadNumber: 16
                                 InputMemorySize: [224 224 3]
                                OutputMemorySize: [112 112 32]
                                FeatureSizeLimit: 1280
    
                          Processing Module "fc"
                                ModuleGeneration: 'on'
                          SoftmaxBlockGeneration: 'off'
                                  FCThreadNumber: 4
                                 InputMemorySize: 1280
                                OutputMemorySize: 1000
    
                       Processing Module "adder"
                                ModuleGeneration: 'on'
                                 InputMemorySize: 40
                                OutputMemorySize: 40
    
                  Processor Top Level Properties
                                  RunTimeControl: 'register'
                              InputDataInterface: 'External Memory'
                             OutputDataInterface: 'External Memory'
                               ProcessorDataType: 'single'
    
                         System Level Properties
                                  TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit'
                                 TargetFrequency: 200
                                   SynthesisTool: 'Xilinx Vivado'
                                 ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
                         SynthesisToolChipFamily: 'Zynq UltraScale+'
                         SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e'
                        SynthesisToolPackageName: ''
                         SynthesisToolSpeedValue: ''
    
    ### Optimizing processor configuration for deep learning network complete.

Version History

Introduced in R2021b