General CRC Generator

Generate CRC code bits according to generator polynomial and append to input data frames

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Libraries:
Communications Toolbox / Error Detection and Correction / CRC

Description

The General CRC Generator block generates cyclic redundancy check (CRC) code bits for each input data frame and appends them to the frame. For more information, see CRC Generator Operation.

Examples

Generate CRC-8 Checksum in Simulink

Generate a CRC-8 checksum for the example shown in 802.11™-2016, section 21.3.10.3 and compare with the expected CRC.

Open Model

Cyclic Redundancy Check Encoding

Append CRC bits to a frame by building a g(x) = x³ + x + 1 generator polynomial using primitive Simulink® blocks and compare the results to the operation of the General CRC Generator block configured for the same generator polynomial.

Open Model

Ports

Input

In — Input signal

binary column vector

Input signal, specified as a binary column vector. The length of the input frame must be a multiple of the value of the Checksums per frame parameter.

Data Types: double | Boolean

Output

Out — Output codeword frame

binary column vector

Output codeword frame, returned as a binary column vector that inherits the data type of the input signal. The output contains the input data frames with the CRC bit sequences appended to them.

The length of the output frame is m + k * r, where m is the size of the input frame, k is the number of checksums per frame, and r is the degree of the generator polynomial.

Parameters

Generator polynomial — Generator polynomial

'z^16 + z^12 + z^5 + 1' (default) | polynomial character vector | binary row vector | integer row vector

Generator polynomial for the CRC algorithm, specified as one of the following:

• A polynomial character vector such as 'z^3 + z^2 + 1'.

• A binary row vector that represents the coefficients of the generator polynomial in order of descending power. The length of this vector is (N+1), where N is the degree of the generator polynomial. For example, [1 1 0 1] represents the polynomial x³+ z²+ 1.

• An integer row vector containing the exponents of z for the nonzero terms in the polynomial in descending order. For example, [3 2 0] represents the polynomial z³ + z² + 1.

For more information, see Representation of Polynomials in Communications Toolbox.

Some commonly used generator polynomials include:

CRC method	Generator polynomial
CRC-32	'z^32 + z^26 + z^23 + z^22 + z^16 + z^12 + z^11 + z^10 + z^8 + z^7 + z^5 + z^4 + z^2 + z + 1'
CRC-24	'z^24 + z^23 + z^14 + z^12 + z^8 + 1'
CRC-16	'z^16 + z^15 + z^2 + 1'
Reversed CRC-16	'z^16 + z^14 + z + 1'
CRC-8	'z^8 + z^7 + z^6 + z^4 + z^2 + 1'
CRC-4	'z^4 + z^3 + z^2 + z + 1'

Example: 'z^7 + z^2 + 1', [1 0 0 0 0 1 0 1], and [7 2 0] represent the same polynomial, p(z) = z ⁷ + z ² + 1.

Initial states — Initial states of internal shift register

0 (default) | 1 | binary row vector

Initial states of the internal shift register, specified as a binary scalar or a binary row vector with a length equal to the degree of the generator polynomial. A scalar value is expanded to a row vector of equal length to the degree of the generator polynomial.

Direct method — Use direct algorithm for CRC checksum calculations

off (default) | on

Select to use the direct algorithm for CRC checksum calculations. When cleared, the block uses the non-direct algorithm for CRC checksum calculations.

For more information on direct and non-direct algorithms, see Error Detection and Correction.

Reflect input bytes — Reflect input bytes

off (default) | on

Select to flip the input data on a bytewise basis before entering the data into the shift register. When Reflect input bytes is selected, the input frame length divided by the value of the Checksums per frame parameter must be an integer and a multiple of 8. When Reflect input bytes is cleared, the block does not flip the input data.

Reflect checksums before final XOR — Reflect checksums before final XOR

off (default) | on

Select to flip the CRC checksums around their centers after the input data are completely through the shift register. When Reflect checksums before final XOR is cleared, the block does not flip the CRC checksums.

Final XOR — Final XOR

0 (default) | 1 | binary row vector

Final XOR, specified as a binary scalar or a binary row vector with a length equal to the degree of the generator polynomial. The XOR operation runs using the value of the Final XOR parameter the CRC checksum before appending the CRC to the input data. A scalar value is expanded to a row vector of equal length to the degree of the generator polynomial. A setting of 0 is equivalent to no XOR operation.

Checksums per frame — Number of checksums calculated for each frame

1 (default) | positive integer

Number of checksums calculated for each frame, specified as a positive integer.

Block Characteristics

Data Types	Boolean | double
Multidimensional Signals	no
Variable-Size Signals	yes

More About

Cyclic Redundancy Check Coding

Cyclic redundancy check (CRC) coding is an error-control coding technique for detecting errors that occur when a data frame is transmitted. Unlike block or convolutional codes, CRC codes do not have a built-in error-correction capability. Instead, when a communications system detects an error in a received codeword, the receiver requests the sender to retransmit the codeword.

In CRC coding, the transmitter applies a rule to each data frame to create extra CRC bits, called the checksum or syndrome, and then appends the checksum to the data frame. After receiving a transmitted codeword, the receiver applies the same rule to the received codeword. If the resulting checksum is nonzero, an error has occurred and the transmitter should resend the data frame.

When the number of checksums per frame is greater than 1, the input data frame is divided into subframes, the rule is applied to each data subframe, and individual checksums are appended to each subframe. The subframe codewords are concatenated to output one frame.

For a discussion of the supported CRC algorithms, see Cyclic Redundancy Check Codes.

CRC Generator Operation

The CRC generator appends CRC checksums to the input frame according to the specified generator polynomial and number of checksums per frame.

For a specific initial state of the internal shift register and k checksums per input frame:

1. The input signal is divided into k subframes of equal size.

2. Each of the k subframes are prefixed with the initial states vector.

3. The CRC algorithm is applied to each subframe.

4. The resulting checksums are appended to the end of each subframe.

5. The subframes are concatenated and output as a column vector.

For the scenario shown here, a 10-bit frame is input, a third degree generator polynomial computes the CRC checksum, the initial state is 0, and the number of checksums per frame is 2.

The input frame is divided into two subframes of size 5 and checksums of size 3 are computed and appended to each subframe. The initial states are not shown, because an initial state of [0] does not affect the output of the CRC algorithm. The output transmitted codeword frame has the size 5 + 3 + 5 + 3 = 16.

References

[1] Sklar, Bernard. Digital Communications: Fundamentals and Applications. Englewood Cliffs, N.J.: Prentice-Hall, 1988.

[2] Wicker, Stephen B. Error Control Systems for Digital Communication and Storage. Upper Saddle River, N.J.: Prentice Hall, 1995.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Version History

Introduced before R2006a