HDL Verifier™ automates the verification of HDL code on Xilinx® FPGA boards by enabling FPGA-in-the-loop (FIL) testing. FIL testing helps ensure that the MATLAB® algorithm or Simulink® design behaves as expected in the real world, increasing confidence in your silicon implementation. The MATLAB algorithm or Simulink model is used to drive FPGA input stimuli and to analyze the output of the FPGA. With FIL testing, you can verify your design at FPGA speeds, enabling you to run more extensive sets of test cases and perform regression tests on your design.
HDL Verifier supports FIL simulation for select Xilinx FPGA boards. The board definition files for these boards are included in the Support Package. You can add other FPGA boards for use with FIL with FPGA board customization.
The following device families are supported:
- Zynq® UltraScale+™ MPSoC
- Virtex® UltraScale, Kintex® UltraScale
- Virtex-7, Kintex-7, Artix®-7, Zynq-7000
- Virtex-6, Spartan®-6
Platform and Release Support
See the hardware support package system requirements table for current and prior version, release, and platform availability.
View enhancements and bug fixes in release notes.