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Results for product_base_code:"HDL Verifier" (209 results)

Results 51 - 100 of 209

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unable to open simulink data inspector

Asked by Bharath Chandan on 9 Oct 2017

Latest activity Commented on by Xiaoyi Zhang on 29 Oct 2022

Real-Time Simulation and Testing Simulink Real-Time Get Started with Simulink Real-Time

1

answer

0 votes
15 views

Mexw64 file not found in matlab foc example

Asked by KW YAN on 30 Jun 2022

Latest activity Commented on by KW YAN on 10 Oct 2022

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
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how to plot HDL cosimulink output

Asked by Niveen Morsi on 2 Mar 2013

Latest activity Answered by Kiran Kintali on 6 Oct 2022

Signal Processing DSP System Toolbox Signal Generation, Manipulation, and Analysis Scopes and Data Logging

1

answer

0 votes
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Not able to generate c code from dpigen

Asked by Shrinish Donde on 31 Aug 2022

Latest activity Answered by David Fink on 4 Sep 2022

Code Generation

1

answer

0 votes
6 views

I2C Master block in SOC FPGA

Asked by Cau Tran on 22 Aug 2022

Latest activity Commented on by Cau Tran on 30 Aug 2022

Accepted Answer by Kiran Kintali

FPGA, ASIC, and SoC Development SoC Blockset System on Chip (SoC)

2

answers

0 votes
10 views

Having issues with connecting Zynq zedboard to computer

Asked by kimi on 14 Jan 2021

Latest activity Answered by Srija Kethiri on 26 Aug 2022

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
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PWM IP core FPGA

Asked by Cau Tran on 3 Aug 2022

Latest activity Answered by Kiran Kintali on 25 Aug 2022

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
31 views

Which ModelSim editions can I use for cosimulation with HDL Verifier?

Asked by MathWorks Support Team on 27 Nov 2019

Latest activity Edited by MathWorks Support Team on 11 Aug 2022

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

2

answers

1 vote
18 views

Where I can get HDL Coder and Embedded Coder for Home license?

Asked by f1y0rdie on 11 Sep 2014

Latest activity Commented on by Xymbu on 30 Jun 2022

Accepted Answer by Shantanu Kedar

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
26 views

Which versions of Xilinx Vivado are supported with which release of HDL Workflow Advisor?

Asked by Onur Dikilitas on 27 Jun 2022

Latest activity Answered by Kiran Kintali on 29 Jun 2022

Code Generation HDL Coder Get Started with HDL Coder

4

answers

0 votes
8 views

Unrecognized function or variable 'vsim'.

Asked by samira sorayaasa on 30 Jul 2021

Latest activity Commented on by Mahdi Naghshvarianjahromi on 24 Jun 2022

Accepted Answer by Kiran Kintali

Code Generation HDL Verifier Verification with Cosimulation MATLAB Cosimulation

1

answer

0 votes
4 views

FPGA in the Loop minimum clock frequency

Asked by Mehmet Sait Eroglu on 7 Jan 2021

Latest activity Answered by Madhu Varshini on 14 Jun 2022

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

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answer

0 votes
2 views

Import HDL Code for HDL Cosimulation Block with VHDL-2008

Asked by Malte on 31 May 2022

Latest activity Answered by Marc Erickson on 2 Jun 2022

Code Generation HDL Coder

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answer

0 votes
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makehdltb. Dont open generated model.

Asked by Tor Hammarbäck on 13 May 2022

Latest activity Answered by Kiran Kintali on 22 May 2022

Code Generation HDL Coder Get Started with HDL Coder

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answers

0 votes
3 views

Can we modify a PCIe AXI Master IP that is unavailable to make it work?

Asked by Nadatimuj on 25 Apr 2022

RF and Mixed Signal Signal Integrity Toolbox Signal Integrity Kits for Industry Standards

1

answer

0 votes
2 views

Assertion failed: B:\matlab\src\cgir_hdl\pir_transforms\PrepareForFunctionCallPartition.cpp:3092:dataType == t

Asked by Adeel Jamal on 24 Mar 2022

Latest activity Answered by Kiran Kintali on 12 Apr 2022

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

1 vote
41 views

Which Xilinx Vivado edition do I need to install for use with HDL Coder, HDL Verifier, or other HDL-related toolboxes?

Asked by MathWorks Support Team on 16 Apr 2020

Latest activity Edited by MathWorks Support Team on 24 Jan 2022

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Get Started with HDL Coder

1

answer

0 votes
8 views

Where i find the registration board files for the ZC706 and FMCOMMS 2/3/4

Asked by George Lucian Chiriac on 16 Dec 2021

Latest activity Answered by Jayadhar Alla on 17 Dec 2021

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
2 views

HDL coder fails generating wavelet denoise function

Asked by Massimiliano Buonamico on 11 Oct 2021

Latest activity Answered by Kiran Kintali on 23 Nov 2021

Code Generation HDL Verifier

2

answers

0 votes
6 views

How to signal divide into windows of lengths [1024] .

Asked by Rasheed Majeed on 16 Nov 2021

Latest activity Answered by Star Strider on 16 Nov 2021

Signal Processing Wavelet Toolbox Discrete Multiresolution Analysis Signal Analysis

1

answer

0 votes
1 view

HDL Verifier Max Bit Width Using System Object

Asked by David on 10 Nov 2021

Latest activity Edited by David on 12 Nov 2021

Accepted Answer by YP

Code Generation HDL Verifier Verification with Cosimulation MATLAB Cosimulation

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answers

0 votes
1 view

ModelSim DE Linux with MATLAB 2021a

Asked by David on 20 Oct 2021

Code Generation HDL Coder

1

answer

0 votes
1 view

How to get my FIL simulation to run faster than pure Simulink

Asked by MathWorks Support Team on 9 Nov 2018

Latest activity Edited by MathWorks Support Team on 27 Sep 2021

Accepted Answer by MathWorks Support Team

Code Generation HDL Verifier Verification with FPGA Hardware FPGA-in-the-Loop

1

answer

0 votes
4 views

Error in FIL simulation at the second time it's running

Asked by Kyoji Marumoto on 14 Sep 2021

Latest activity Edited by Kyoji Marumoto on 21 Sep 2021

Code Generation HDL Verifier Verification with FPGA Hardware FPGA-in-the-Loop

2

answers

0 votes
3 views

Control the gain variable inside the generated IP block

Asked by Anoop R on 6 Sep 2021

Latest activity Answered by JT Ferrara on 8 Sep 2021

Accepted Answer by JT Ferrara

FPGA, ASIC, and SoC Development Vision HDL Toolbox HDL Code Generation and Deployment

1

answer

0 votes
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How to switch to visualize the output of FFT HDL Optimized in the frequency domain ?

Asked by Youssef Abdelsalam on 30 Aug 2021

Latest activity Commented on by Youssef Abdelsalam on 31 Aug 2021

Signal Processing DSP System Toolbox Transforms and Spectral Analysis Transforms

1

answer

0 votes
1 view

Why is the output of the FFT HDL Optimized block zeros in Vivado's Simulation ?

Asked by Youssef Abdelsalam on 19 Aug 2021

Latest activity Commented on by Youssef Abdelsalam on 24 Aug 2021

Accepted Answer by Bharath Venkataraman

Signal Processing DSP System Toolbox Transforms and Spectral Analysis Transforms

1

answer

0 votes
5 views

how to solve coder.internal.Float2FixedConverter.runTestBenchToLogDataNew ?

Asked by Facundo Picco on 17 Aug 2021

Latest activity Answered by Marc Erickson on 18 Aug 2021

Accepted Answer by Marc Erickson

Code Generation HDL Verifier ASIC Testbench DPI Generation for MATLAB Code

1

answer

0 votes
5 views

How to implement a real-time fft for FPGA with matlab or simulink ?

Asked by Youssef Abdelsalam on 13 Aug 2021

Latest activity Commented on by Youssef Abdelsalam on 16 Aug 2021

Accepted Answer by Bharath Venkataraman

Signal Processing DSP System Toolbox Transforms and Spectral Analysis Transforms

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answers

0 votes
13 views

Running Cosimulation with QuestaSim

Asked by Heston Jayasinghe on 29 Jul 2021

Latest activity Edited by Heston Jayasinghe on 2 Aug 2021

MATLAB Installation and Licensing Downloads

1

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0 votes
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How do i design a synthesizable FFT with Simulink or Matlab for later on FPGA Implementation ?

Asked by Youssef Abdelsalam on 14 Jul 2021

Latest activity Commented on by Youssef Abdelsalam on 16 Jul 2021

Signal Processing DSP System Toolbox Transforms and Spectral Analysis Transforms

1

answer

0 votes
1 view

Serial communication through Matlab

Asked by Jim on 31 May 2013

Latest activity Answered by Kiran Kintali on 1 Jul 2021

Code Generation HDL Verifier Verification with Cosimulation MATLAB Cosimulation

1

answer

0 votes
2 views

AXI4 Speedgoat Target Machine Data Streaming

Asked by Edmond Hameli on 3 Dec 2019

Latest activity Edited by Dimitri MANKOV on 22 Jun 2021

Real-Time Simulation and Testing Simulink Real-Time System Configuration Target Computer Setup

0

answers

0 votes
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Question on error message: "The compiled entry-point 'FIFO_Buffer_hdl_mex' cannot be located."

Asked by Yufei Zhang on 2 Jun 2021

Code Generation HDL Verifier ASIC Testbench DPI Generation for MATLAB Code

1

answer

0 votes
2 views

Can Matlab R2018b use the Kintex7 board from a X310 USRP and, if so, how?

Asked by Wayne Walker on 22 Jan 2019

Latest activity Answered by Kiran Kintali on 24 May 2021

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
2 views

Best Practices for Simulink HDL Coder Development

Asked by Philippe on 16 Apr 2013

Latest activity Answered by Kiran Kintali on 24 May 2021

Signal Processing DSP System Toolbox Code Generation HDL Code Generation

1

answer

0 votes
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How to prepare FPGA board for MATLAB

Asked by Thomas on 4 Jun 2014

Latest activity Answered by Kiran Kintali on 24 May 2021

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
0 views

MATLAB as AXI master and FIL tool at the same time

Asked by dr446 on 26 Feb 2019

Latest activity Answered by Kritika Bhardwaj on 20 May 2021

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
1 view

Running HDL Verifier DataCapture on Linux Machine?

Asked by Nicholas Peng on 13 Feb 2019

Latest activity Answered by Kritika Bhardwaj on 20 May 2021

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
6 views

How to do FPGA-in-the-loop simulation with Altera DE2-115 board?

Asked by Michael Roth on 18 Jan 2013

Latest activity Commented on by Mohamed BAGHDADI on 17 May 2021

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
1 view

dpigen testbench : Error using coder.internal.Float2FixedConverter

Asked by Yufei Zhang on 3 May 2021

Latest activity Answered by Shiva Kalyan Diwakaruni on 6 May 2021

Accepted Answer by Shiva Kalyan Diwakaruni

MATLAB App Building Develop Apps Using App Designer

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answers

0 votes
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dpigen: "??? Error evaluating the post-code-generation command"

Asked by Alvin Tung on 3 May 2021

Latest activity Commented on by Tianqi Liu on 4 May 2021

Code Generation HDL Coder

0

answers

0 votes
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How to workaround with limitation that dpigen does not support variable sized data for Input/Output?

Asked by Yufei Zhang on 29 Apr 2021

Latest activity Commented on by Walter Roberson on 3 May 2021

MATLAB Environment and Settings

2

answers

0 votes
1 view

Does HDL Verifier support FPGA-in-the-loop for BEECube MiniBEE?

Asked by MathWorks Support Team on 21 Aug 2015

Latest activity Edited by MathWorks Support Team on 19 Apr 2021

Accepted Answer by MathWorks Support Team

FPGA, ASIC, and SoC Development Vision HDL Toolbox Video Formats and Interfaces

4

answers

0 votes
10 views

Failed to initialize the RTIOStream library during FPGA-in-the-loop simulation

Asked by Bo Zhang on 9 Mar 2016

Latest activity Edited by emanuel Murillo on 2 Apr 2021

Accepted Answer by Tao Jia

Code Generation HDL Coder Get Started with HDL Coder

1

answer

0 votes
0 views

Latch logic is detected for variable 'start_token', failed to import Simulink model. Hdl Import parse failed.

Asked by Khalala Mamouri on 26 Mar 2021

Latest activity Commented on by Khalala Mamouri on 26 Mar 2021

Code Generation HDL Coder Get Started with HDL Coder

2

answers

0 votes
12 views

Timed out on waiting for AXI write response.

Asked by Praneet Kala on 28 Sep 2020

Latest activity Answered by Nadatimuj on 26 Feb 2021

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
3 views

Coverage in FPGA in the loop

Asked by Ander Albizu on 19 Jan 2021

Latest activity Commented on by Ander Albizu on 1 Feb 2021

Code Generation

2

answers

0 votes
6 views

zedboard fpga in loop

Asked by irem on 20 Aug 2015

Latest activity Commented on by Eduardo Flores on 29 Nov 2020

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
6 views

"Error: Synthesis failed", "HDL compilation failed"

Asked by andrew kurtz on 26 Nov 2018

Latest activity Edited by xioabo li on 20 Nov 2020

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

Results 51 - 100 of 209