Not getting desired waveform when using the hdl supported free running counter

I have generated a sine pwm using sine-triangle comparison method. The sawtooth waveform is generated by a free running (HDL supported)counter with 6-bit. The stepped waveform generated contains only six or seven steps, this I believe incorrect. For a six bit counter, I expect a stepped sawtooth waveform with 64 steps, but I am getting only 6 to 7 stepped sawtooth waveform (Amplitude > 60)!!

Any idea what problem it is?

The solver used is fixed and discrete. This is selected because I want to convert the model into HDL code (Verilog code).

Any further details required..

Regards,

Answer 1

[Tim McBrayer]

The HDL Counter has (among other mask parameters) initial value, step value, and count to value. I think you are confusing the count to value with counter bit width. if you want a 64-value counter, one way to configure it is with a start value of 0, a stop value of 63, and an increment of 1. The numeric type for the counter's output is an entirely separate set of configurable mask parameters.