Model losses in Switched-Capacitor DC-DC Converter
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Good day to all.
I'm trying to do some power loss modeling for SC DC-DC converters. I am starting out with an ideal model with constant on-resistance switches and will be gradually adding non-idealities to the switches, ADC (for feedback), and clocks. Any idea on how to model gate drive loss if I were driving MOSFETs for switches?
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