Serial port send/receive order

Hello,

I have a problem with Stream Output (SO) and Stream Input (SI) block execution order when running my model in external mode on Real-Time Windows Target. The idea is that the model produces some data, sends it to microcontroller (uC) through serial port (SO block) and receives uC’s response (SI block) in the same simulation step. I tried to ensure that sending occurs before receiving by setting Priority property of SO and SI blocks.

In the first test I configured the model to send one character at each step and the uC to simply echo the characters. Problem is that the model receives uC responses with one step delay. If the model sends [‘1’, ‘2’, ‘3’…], it receives [‘0’, ‘1’, ‘2’ …]. Data Ready output of the SI block is false in the first step, and true in all subsequent ones.

I tried few things to resolve the issue:

1. I observed Rx and Tx lines of the serial connection by oscilloscope and validated that uC echoes received characters correctly. It responds with few microseconds delay which shouldn’t be a problem if simulation step size is 100 ms.
2. I tried to force simulation to wait a bit after sending data and before trying to receive but I didn’t find a way to do this. Is there really no way to say to rtwin external simulation to wait e.g. for 5us during 100ms step?
3. I tried putting SI block inside do-while loop implemented by While Iterator subsystem that executes until SI’s Data Ready output becomes true. If I limit the number of iterations the loop executes for the set number in the first step without receiving. In subsequent steps it receives one step old response in the first loop iteration. If number of iterations is unlimited, infinite loop (i.e. blue screen of death) occurs when I run the simulation.
4. By inspecting generated rtwin C code I observed that SO’s code for sending data resides in model update function and SI’s code for receiving is in model output function. If I’m not mistaken, model outputs are always computed before the model states are updated so that SI receives before SO sends data. In the first step when SI tries to receive nothing has yet been sent/echoed so there is no data to receive. Is my reasoning correct?
5. By rearranging rtwinso.tlc file, that determines how code is generated for SO block, I moved the code for sending to model output function. With SI in do-while loop one-step delay is again present.

Appreciate any help, Josip