For a MATLAB to HDL code project, you should be able to divide your code into your design (that will ultimately be placed on a FPGA) and the testbench code. The testbench code will read the data, perhaps process it in some fashion, and invoke the DUT, passing it the appropriate data. It will also read back the results and perform any necessary validation to verify (in MATLAB) that the design is working properly. The code that makes up the testbench is completely unrestricted; any MATLAB code, such as wavread, may be placed in the MATLAB testbench code.
Once you have your code partitioned in this fashion you can generate HDL code fro the design. You can also generate a HDL testbench, which will pass the input data recorded from the MATLAB simulation to the design, and verify that the design outputs match those recorded from the MATLAB run.
If you also have the HDL Verifier product you can co-simulate your generated HDL design directly in your MATLAB test bench. HDL Verifier also allows you to perform a FPGA-in-loop simulation, where your design is programmed into the FPGA on one of a set of supported hardware boards, and simulated in lock-step with your original MATLAB testbench.
