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Prototype LTE Algorithms on Hardware

The Communications Toolbox™ Support Package for Xilinx® Zynq®-Based Radio enables you to design, prototype, and verify practical wireless communications systems on Xilinx Zynq-based radio hardware.

  • Use the Xilinx Zynq-based radio as an I/O peripheral to transmit and receive real-time arbitrary waveforms using MATLAB® System objects or Simulink® blocks.

  • Transmit and receive RF signals out of the box, enabling quick testing of SDR designs under real-world conditions.

  • Transmit and receive data on one or two channels.

  • Configure RF radio settings easily.

  • Acquire high-bandwidth signals by using burst mode.

  • In Simulink, customize and prototype SDR algorithms. Target only the FPGA fabric of the device, or deploy partitioned hardware-software co-design implementations across the ARM® processor and the FPGA fabric of the device (Windows® operating system only).

  • Run application examples to get started.

The support package provides two workflows:

  • FPGA-only targeting – This workflow uses generated HDL code from HDL Coder™ and HDL Coder Support Package for Xilinx Zynq Platform.

  • Hardware-software co-design – This workflow also uses HDL Coder and HDL Coder Support Package for Xilinx Zynq Platform. It additionally requires Simulink Coder™, Embedded Coder®, and Embedded Coder Support Package for Xilinx Zynq Platform.

The LTE MIB Recovery and Cell Scanner Using Analog Devices AD9361/AD9364 (Communications Toolbox Support Package for Xilinx Zynq-Based Radio) support package example shows how to use the hardware-software co-design workflow to deploy the design from LTE HDL MIB Recovery to a hardware board with a radio daughter card. The LTE Receiver Using Analog Devices AD9361/AD9364 (Communications Toolbox Support Package for Xilinx Zynq-Based Radio) support package example shows how to capture live LTE data for use in testing your designs.

How to Install Support Packages

A support package is an add-on that enables you to use a MathWorks® product with specific third-party hardware and software. Support packages use the license of the base product. For instance, Communications Toolbox Support Package for Xilinx Zynq-Based Radio requires a license for Communications Toolbox.

Install support packages using the MATLAB Add-Ons menu. You can also use the Add-Ons menu to update installed support package software or update the firmware on third-party hardware.

To install support packages, on the MATLAB Home tab, in the Environment section, click Add-Ons > Get Hardware Support Packages. You can filter this list by selecting categories (such as hardware vendor or application area), or by performing a keyword search.

Search the Add-Ons list for Zynq, and install these support packages:

  • Communications Toolbox Support Package for Xilinx Zynq-Based Radio

  • HDL Coder Support Package for Xilinx Zynq Platform

  • Embedded Coder Support Package for Xilinx Zynq Platform (only needed for hardware-software co-design)

When the support package installation is complete, you must set up the host computer and radio hardware. For Windows systems, the installer provides guided setup steps. For Linux® systems, the installer links to manual setup instructions.

Design Requirements

The Communications Toolbox Support Package for Xilinx Zynq-Based Radio provides a reference design that you can use to create an IP core that integrates into the radio hardware. Use the HDL Workflow Advisor to guide you through generating a shareable and reusable IP core module using the reference design.

To work with the reference design, your FPGA targeted design must use a streaming data interface with a control signal that indicates the validity of each sample. Wireless HDL Toolbox™ blocks provide this interface. Use the Sample Control Bus Selector block to separate the valid control signal from the bus.

To deploy a design using the support package, your design must meet these preconditions.

  • Each data input or output must be 16 bits. The HDL subsystem that fits into the reference design does not support complex signals at the ports. To handle complex inputs and outputs, model separate I and Q ports at the subsystem boundaries.

  • Model all the ports for a given reference design, even when the ports are not used.

  • In Simulink, the input and output data and valid signals must be driven at the same sample rate. Therefore, the input and output clock rates of the subsystem must be equal.

  • Clock the data and valid signals at the fastest rate of the HDL subsystem.

  • For the FPGA-only targeting workflow:

    • Duplex operation is not supported. Use either the transmit or the receive operation, but not both.

  • For the hardware-software co-design workflow:

    • Duplex operation is supported. You can use both the Transmitter and Receiver blocks in the same design.

    • AXI4-Lite register ports can be clocked at arbitrary rates.

    • In single-channel mode, you can transmit or receive data frames containing an even number of samples only. If you use an odd number of samples, the software inserts a zero sample at the end of each frame.

The real-time design encounters a larger volume of data and a larger set of state progressions than you can simulate in Simulink. Make sure to model and generate control logic to handle the restart between subframes. Consider adding extra subsystem ports for debug visibility of these extended states once the design is deployed to the board.

Design for Debugging

Once the design is deployed to the board, you have much less visibility of the internal signals in your design. To improve visibility, you can add temporary output ports to your subsystem before you generate your IP core. Signals that can help with debugging are design state, mux select signals or other control parameters, and data values at intermediate stages of the data path. You can also add input ports and muxes to give the option for external control of parameters such as mux select signals and gain values.

When you simulate the design on the board in External mode, you can drive and view these ports from Simulink. The Xilinx Zynq AXI Interface block from the generated software model provides a Simulink interface to the input and output ports of your design while it is running on the board.

Once you are confident that your design is behaving as intended, you can remove these ports and regenerate the IP core.

Another debugging strategy is to include a known input signal stored in memory on the FPGA. This memory can be part of the generated HDL code from your Simulink model. The LTE MIB Recovery and Cell Scanner Using Analog Devices AD9361/AD9364 (Communications Toolbox Support Package for Xilinx Zynq-Based Radio) support package example shows an input port externalDataSel that provides a switch between a stored data set and the live data from the radio.

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