Deploy Satellite Communications HDL Reference Applications on FPGAs and SoCs

This section contains the list of examples that show how to deploy satellite communications Wireless HDL Toolbox™ reference applications on FPGAs and SoCs.

• DVB-S2 HDL PL Header Recovery Using Analog Devices AD9361/AD9364 (SoC Blockset): Deploy a DVB-S2 time, frequency, and phase synchronization and PL header recovery algorithm.

• DVB-S2 Receive Using AMD RFSoC Device (SoC Blockset): Deploy a DVB-S2 transmit and receive algorithm.

• GPS Acquisition Using AMD RFSoC Device (SoC Blockset): Deploy a GPS acquisition algorithm.

These examples reuse the satellite communication Simulink® models to generate HDL for the FPGA logic. They use hardware-software co-design modeling techniques and hardware support packages to add all the software modeling and interfacing required to implement the algorithm in real-time on hardware.

Related Topics

• DVB-S2 HDL Receiver
• DVB-S2 HDL PL Header Recovery