Buffer input stream to create image lines that have contiguous valid pixels
Vision HDL Toolbox / Utilities
The Pixel Stream FIFO block stores incoming valid pixels and accompanying control signals and returns the same pixel stream without gaps between the valid pixels of each line. The block preserves the total line size and total frame size of the video stream, including invalid cycles.
Use the Pixel Stream FIFO block to buffer video sources. The waveform shows a direct memory access (DMA) video source, where pixels are read in bursts, and a Camera Link® video source, where pixels are valid every second clock cycle. To create contiguous video lines, a Pixel Stream FIFO block buffers the input pixels and control signals of each source.
This block uses a streaming pixel interface with a bus for
frame control signals. This interface enables the block to operate independently of image size
and format. The pixel ports on this block support single pixel streaming or
multipixel streaming. Single pixel streaming accepts and returns a single pixel value each clock
cycle. Multipixel streaming accepts and returns 4 or 8 pixels per clock cycle to support
high-frame-rate or high-resolution formats. Along with the pixel, the block accepts and returns
a pixelcontrol
bus that contains five control signals. The control signals
indicate the validity of each pixel and their location in the frame. For multipixel streaming,
one set of control signals applies to all four or eight pixels in the vector. To convert a frame
(pixel matrix) into a serial pixel stream and control signals, use the Frame
To Pixels block. For a full description of the interface, see Streaming Pixel Interface.
This block also supports multipixel-multicomponent streams, where the pixel input is a matrix of M-by-N values, where M is number of pixels and N is number of components. These values correspond to the Number of pixels and Number of components parameters of the Frame To Pixels block.
The Pixel Stream FIFO block contains a memory controller, read and
write counters, and two RAMs. One RAM stores the incoming control signals, and the other
stores the incoming pixel stream. The block stores valid pixels and their accompanying
control signals for each line, as determined by the input
ctrl.hStart
and
ctrl.hEnd
signals. The buffering removes any
bursty behavior of the input stream. Once a full line of valid pixels is stored, the
block returns the new continuous version of the line.
When the input pixel is a vector or a matrix, the block replicates the Pixel RAM for each element. The diagram shows three Pixel RAMs, to represent a three-component pixel stream. For multipixel streaming, the block adjusts the line buffer size to store 1/Number of pixels pixels. For instance, with a 4-by-3 input stream, each buffer stores ¼ of the pixels for a line, so there are 12 Pixel RAMs, each with 2m-2 locations.