Pixel Stream FIFO

Buffer input stream to create image lines that have contiguous valid pixels

• Library:

• Vision HDL Toolbox / Utilities

• 

Description

The Pixel Stream FIFO block stores incoming valid pixels and accompanying control signals and returns the same pixel stream without gaps between the valid pixels of each line. The block preserves the total line size and total frame size of the video stream, including invalid cycles.

Use the Pixel Stream FIFO block to buffer video sources. The waveform shows a direct memory access (DMA) video source, where pixels are read in bursts, and a Camera Link^® video source, where pixels are valid every second clock cycle. To create contiguous video lines, a Pixel Stream FIFO block buffers the input pixels and control signals of each source.

Ports

This block uses a streaming pixel interface with a bus for frame control signals. This interface enables the block to operate independently of image size and format. The pixel ports on this block support single pixel streaming or multipixel streaming. Single pixel streaming accepts and returns a single pixel value each clock cycle. Multipixel streaming accepts and returns 4 or 8 pixels per clock cycle to support high-frame-rate or high-resolution formats. Along with the pixel, the block accepts and returns a pixelcontrol bus that contains five control signals. The control signals indicate the validity of each pixel and their location in the frame. For multipixel streaming, one set of control signals applies to all four or eight pixels in the vector. To convert a frame (pixel matrix) into a serial pixel stream and control signals, use the Frame To Pixels block. For a full description of the interface, see Streaming Pixel Interface.

This block also supports multipixel-multicomponent streams, where the pixel input is a matrix of M-by-N values, where M is number of pixels and N is number of components. These values correspond to the Number of pixels and Number of components parameters of the Frame To Pixels block.

Input

pixel — Input pixel stream

scalar | vector | matrix

For scalar pixel streams, specify pixel as a scalar or a vector of 1-by-Number of components values. For multipixel streams, specify pixel as a matrix of Number of pixels-by-Number of components pixel intensity values.

double and single data types are supported for simulation, but not for HDL code generation.

Data Types: fixed point | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean | double | single

ctrl — Control signals associated with pixel stream

pixelcontrol bus

The pixelcontrol bus contains five signals. The signals describe the validity of the pixel and its location in the frame. For more information, see Pixel Control Bus.

For multipixel streaming, each vector of pixel values has one set of control signals. Because the vector has only one valid signal, the pixels in the vector must be either all valid or all invalid. The hStart and vStart signals apply to the pixel with the lowest index in the vector. The hEnd and vEnd signals apply to the pixel with the highest index in the vector.

Data Types: bus

Output

pixel — Pixel stream

scalar | vector | matrix

Each line of the output stream has contiguous valid pixels. The dimensions and data type of the output pixel stream match those of the input pixel stream. The block returns the output pixel stream as a scalar, a vector of 1-by-Number of components values, or a matrix of Number of pixels-by-Number of components values.

ctrl — Control signals accompanying pixel stream

pixelcontrol bus

Control signals accompanying pixel stream, returned as a pixelcontrol bus containing five signals. The signals indicate the validity of the pixel and its location in the frame. For more information on the signal protocol, see Pixel Control Bus.

The Pixel Stream FIFO block returns each line of pixels with the ctrl.valid signal continuously true between ctrl.hStart and ctrl.hEnd. The block buffers the entire input line before it returns the modified line.

Data Types: bus

Parameters

Line buffer size — Size of line memory buffer

2048 (default) | positive integer

Specify a power of two that accommodates the number of active pixels in a single horizontal line. If you specify a value that is not a power of two, the block uses the next largest power of two.

Model Examples

Buffer Bursty Data Using Pixel Stream FIFO Block

Interface with bursty pixel streams, such as those from DMA and Camera Link® sources, using the Pixel Stream FIFO block.

Algorithms

The Pixel Stream FIFO block contains a memory controller, read and write counters, and two RAMs. One RAM stores the incoming control signals, and the other stores the incoming pixel stream. The block stores valid pixels and their accompanying control signals for each line, as determined by the input ctrl.hStart and ctrl.hEnd signals. The buffering removes any bursty behavior of the input stream. Once a full line of valid pixels is stored, the block returns the new continuous version of the line.

When the input pixel is a vector or a matrix, the block replicates the Pixel RAM for each element. The diagram shows three Pixel RAMs, to represent a three-component pixel stream. For multipixel streaming, the block adjusts the line buffer size to store 1/Number of pixels pixels. For instance, with a 4-by-3 input stream, each buffer stores ¼ of the pixels for a line, so there are 12 Pixel RAMs, each with 2^m-2 locations.

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation

Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Restrictions

You cannot generate HDL for this block inside an Enabled Subsystem (Simulink), Resettable Synchronous Subsystem (HDL Coder), or a Triggered Subsystem (Simulink).