Actual code generation support depends on block implementation.
HDL Coder™ provides additional configuration options that affect HDL
implementation and synthesized logic.
Best PracticesWhen using enabled subsystems in models targeted for HDL code generation, it
is good practice to consider the following:
For synthesis results to match Simulink® results, the Enable port must be driven by registered
logic (with a synchronous clock) on the FPGA.
Put unit delays on Enabled Subsystem output signals. Doing so prevents
the code generator from inserting extra bypass registers in the HDL
code.
Enabled subsystems can affect synthesis
results in the following ways:
In some cases, the system clock speed can drop by a small
percentage.
Generated code uses more resources, scaling with the number of
enabled subsystem instances and the number of output ports per
subsystem.
HDL Architecture| Architecture | Description |
|---|
Module (default) | Generate code for the subsystem and the blocks within the subsystem. |
BlackBox | Generate a black box interface. The generated HDL code
includes only the input/output port definitions for the subsystem.
Therefore, you can use a subsystem in your model to generate an interface
to existing, manually written HDL code. The black-box
interface generation for subsystems is similar to the Model block
interface generation without the clock signals. |
No HDL
| Remove the subsystem from the generated code. You can
use the subsystem in simulation, however, treat it as a “no-op”
in the HDL code. |
HDL Block Properties| General |
|---|
| AdaptivePipelining | Automatic pipeline insertion based on the synthesis tool, target frequency, and
multiplier word-lengths. The default is inherit. See also
AdaptivePipelining (HDL Coder).
|
| BalanceDelays | Detects introduction of new delays along one path and inserts
matching delays on the other paths. The default is inherit.
See also BalanceDelays (HDL Coder).
|
| ClockRatePipelining | Insert pipeline registers at a faster clock rate instead of the slower data rate. The
default is inherit. See also ClockRatePipelining (HDL Coder).
|
| ConstrainedOutputPipeline | Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is
0. For more details, see ConstrainedOutputPipeline (HDL Coder).
|
| DistributedPipelining | Pipeline register distribution,
or register retiming. The default is inherit. See
also DistributedPipelining (HDL Coder).
|
| DSPStyle | Synthesis attributes for multiplier mapping. The default is none.
See also DSPStyle (HDL Coder).
|
| FlattenHierarchy | Remove subsystem hierarchy from generated HDL code. The default
is inherit. See also FlattenHierarchy (HDL Coder).
|
| InputPipeline | Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
0. For more details, see InputPipeline (HDL Coder).
|
| OutputPipeline | Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
0. For more details, see OutputPipeline (HDL Coder).
|
| SharingFactor | Number of functionally equivalent resources to map to a single
shared resource. The default is 0. See also Resource Sharing (HDL Coder).
|
| StreamingFactor | Number of parallel data paths, or vectors, that are time multiplexed
to transform into serial, scalar data paths. The default is 0, which
implements fully parallel data paths. See also Streaming (HDL Coder).
|
Target Specification
This block cannot be the DUT, so the block property settings in the Target
Specification tab are ignored.
RestrictionsHDL Coder supports HDL code generation for enabled subsystems that meet the
following conditions:
The enabled subsystem is not the DUT.
The subsystem is not both triggered
and enabled.
The enable signal is a scalar.
The input datatype for the enable signal is boolean.
If the output of the subsystem is a bus then Initial
condition of the outport must be 0.
All inputs and outputs of the enabled
subsystem (including the enable signal) run at the same rate.
The Show output port parameter of the Enable
block is set to Off.
The States when enabling parameter of the Enable
block is set to held (i.e., the Enable block
does not reset states when enabled).
The Output when disabled parameter for the
enabled subsystem output ports is set to held
(i.e., the enabled subsystem does not reset output values when
disabled).
If the DUT contains the following blocks,
RAMArchitecture is set to
WithClockEnable:
Dual Port RAM
Simple Dual Port RAM
Single Port RAM
The enabled subsystem does not contain the following blocks:
ExampleThe Automatic Gain Controller example shows how you can use enabled subsystems
in HDL code generation. To open the example, enter:
Actual data type support depends on block implementation.
