Main Content

RFDC Bus Selector

Convert RF Data Converter real-time interface-compatible bus into control signals

  • Library:
  • SoC Blockset Support Package for Xilinx Devices / SDR / RFDataConverter

  • RFDC Bus Selector block

Description

The RFDC Bus Selector block separates an RF Data Converter real-time interface-compatible bus into a set of control signals. The block accepts a bus and outputs control signals.

Ports

Input

expand all

Input control bus, specified as a bus.

Data Types: RFDC2DUTRealTimeCtrlBusObj

Output

expand all

Over range output, returned as a Boolean scalar. A High on this output indicates that the signal exceeds the full-scale input of the digital-to-analog converter (DAC) or analog-to-digital converter (ADC).

Data Types: Boolean

Over threshold 1 output, returned as a Boolean scalar. A High on this output indicates that the signal amplitude level exceeds the threshold value specified by the Threshold1 parameter in the RF Data Converter block.

Data Types: Boolean

Over threshold 2 output, returned as a Boolean scalar. A High on this output indicates that the signal amplitude level exceeds the threshold value specified by the Threshold2 parameter in the RF Data Converter block.

Data Types: Boolean

Over voltage output, returned as a Boolean scalar. An Over Voltage condition occurs when a signal far exceeds the normal operating input-range. For more information, see Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3 in the Xilinx® documentation.

Data Types: Boolean

Common mode over voltage output, returned as a Boolean scalar. A High on this output indicates that the input signal common mode exceeds the safe operating conditions. For more information, see Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3 in the Xilinx documentation.

Dependencies

To enable this port, select Gen 3.

Data Types: Boolean

Common mode under voltage output, returned as a Boolean scalar. A High on this output indicates that the input signal common mode is too low for safe operation. For more information, see Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3 in the Xilinx documentation.

Dependencies

To enable this port, select Gen 3.

Data Types: Boolean

Parameters

expand all

Select this parameter to add ports for Gen 3 Zynq® UltraScale+™ RFSoC devices.

Extended Capabilities

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Version History

Introduced in R2022a