Reference Design for Zynq-7000 and MPSoC Devices

SoC Blockset™ provides the Default System with SoC Blockset reference design for the supported Zynq^®-7000 and MPSoC devices. This reference design supports high-speed data streaming applications.

Generate an IP core for a design under test (DUT) and integrate the generated IP core into the Default System with SoC Blockset reference design. Connect the IP core with rest of the design by using the AXI4-Stream to software, software to AXI4-Stream, AXI4 Master, interrupt, or AXI4-Lite interfaces. The figure shows how the interfaces connect the processor to the DUT:

Supported Interface Methods

You can use the Default System with SoC Blockset reference design with these interfaces:

• Register Interface (AXI4-Lite or AXI4) — Use this interface to access the control and status registers in your design. You can choose between AXI4-Lite or AXI4 protocol for the register interface. Use AXI4-Lite if you need only lightweight data transfers. Use AXI4 to connect to components that support burst data transfers. For more information, see Register Interface (AXI4-Lite/AXI4) (HDL Coder).

• AXI4 Master — Use this interface for designs that require you to access memory, or to control other IP cores with AXI4 or AXI4-Lite interfaces. Example applications include moving large amounts of data between your algorithm and external DDR memory. For more information, see AXI4 Master (HDL Coder).

• AXI4-Stream — Use this interface for moving streaming data or transferring data at high speeds. Example applications include transferring large amounts of data between processors and FPGAs using direct memory access (DMA). For more information, see AXI4-Stream (HDL Coder).

• External I/O and External Port — Use this interface to connect to peripherals on your hardware board, such as LEDs, push buttons, DIP switches, FPGA pins, and so on. For more information, see External I/O and External Port (HDL Coder).

• FPGA Data Capture — Use this interface to capture raw data from outputs or signals by using test points in your design and then use the data to debug your design. For more information, see FPGA Data Capture (HDL Coder).

• Interrupt — Use this interface to send interrupt signal from DUT to processor to trigger an event-driven task.

Supported Boards

You can use the Default System with SoC Blockset reference design architecture with these target platforms:

• Xilinx^® Zynq ZC706 Evaluation Kit

• ZedBoard™

• Xilinx Zynq UltraScale+™ MPSoC ZCU102 Evaluation Kit

• Xilinx Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit

Target Algorithm to Reference Design

To target your algorithm in Simulink^® to the Default System with SoC Blockset reference design:

1. Model your algorithm.

2. On the HDL Code tab of the Simulink toolstrip, in the Output section, set the drop-down button to IP Core.

3. Select your DUT and make sure that Code for is set to this DUT.

4. Open the HDL Code Generation > Target tab of the Configuration Parameters dialog box by clicking the Settings button.

5. Set Target Platform to a supported hardware board listed in Supported Boards. Ensure that the Synthesis Tool is set to Xilinx Vivado.

6. Set Reference Design to Default System with SoC Blockset.

   

Set Reference Design Parameters

In the Configuration Parameters dialog box, on the HDL Code Generation > Target tab, set reference design parameters to the required values. The Default System with SoC Blockset reference design has these configuration parameters:

• AXI stream to software data width — Specify data width for AXI4-Stream to software interface as 32, 64, or 128 bits.

• Software to AXI stream data width — Specify data width for software to AXI4-Stream interface as 32, 64, or 128 bits.

• FPGA Data Capture (HDL Verifier required) — Generate and integrate the data capture IP into the reference design. Use FPGA data capture to observe signals from your design while the design is running on the FPGA. This feature captures a window of signal data from the FPGA and returns the data to MATLAB^® or Simulink over a JTAG connection. To capture data over a JTAG connection, set this parameter to JTAG. To capture data over an Ethernet connection, set this parameter to PL Ethernet. Then, map each signal that you want to capture to the FPGA Data Capture interface.

  Note

  • FPGA data capture in Configuration Parameters support programmable logic (PL) Ethernet only. The processing system (PS) Ethernet is not supported.

  • To enable the PL Ethernet option for the Xilinx boards that have the Ethernet physical layer (PHY), manually add the Ethernet media access controller (MAC) Hub IP in the plugin_board file using the addEthernetMACInterface (HDL Coder) method before you open the Configuration Parameters dialog box.

  • FPGA data capture in Configuration Parameters does not support SGMII interface.

Map DUT Ports

To automatically map the DUT ports to the required interfaces, on the System on Chip tab, click Map Interfaces. You can view and edit the interface mapping by following these steps:

1. On the HDL Code tab, click Target Interface to open the IP Core editor.

2. Select the Interface Mapping tab to map each DUT port to one of the IP core target interfaces. If no mapping table appears, click the Reload IP core settings button to compile the model and repopulate the DUT ports and their data types.

3. Validate your settings by clicking the Validate IP core settings button.

Generate IP Core and Program FPGA

Generate the IP core and the FPGA bitstream file. Then, program the FPGA by following these steps:

1. In the Simulink toolstrip, on the HDL Code tab, click Build Bitstream to generate the IP core and bitstream file. Wait until the synthesis tool runs in the external window.

2. Expand the Build Bitstream menu. Then, select Program Target Device to download the bitstream.

Generate Host Interface Script

Verify the generated IP core on the hardware board by using the generated host interface script. This script contains the DUT ports and interface mapping information. Use this script to access the board memory, DUT registers, and AXI4-Stream interfaces from MATLAB. To generate a host interface script file, in the Simulink toolstrip, on the HDL Code tab, expand the Host Interface Script menu. Then, select Host Interface Script. This option generates these MATLAB files:

• gs_modelName_setup — This script adds the AXI4 slave, AXI4-Stream, and memory interfaces. The script also contains DUT port objects that contain the port name, direction, data type, and interface mapping information. The script then maps the DUT ports to the corresponding interfaces.

• gs_modelName_interface — This script creates a target object, instantiates the setup script gs_modelName_setup, and then connects to the target hardware. The script then sends read and write commands to the generated HDL IP core.

For more information about host interface script, see Host Interface Script Files (HDL Coder).

Generate Software Interface Model

To target your hardware board, you can generate a software model in addition to the FPGA model. This action generates two models: a hardware interface model and a software interface model. It also generates two libraries that contain the interface blocks used in the generated models.

The software interface model and its library are generated only if you have Embedded Coder^® and SoC Blockset Support Package for AMD FPGA and SoC Devices installed.

• You can use the hardware interface model to control the reference design on the board, including IP core, from the Simulink model, without Embedded Coder.

• The software interface model enables you to target your software algorithms to the ARM^® processor on the board.

For more information about software interface model, see Generate SoC Software Model.