Tests for Subsystems and Referenced Models
Tests for Subsystems and Referenced Models in Simulink® Design Verifier™ refers to the capability of the tool to generate test cases specifically for individual subsystems and referenced models within a larger Simulink model. This feature allows users to focus on specific components of a model, ensuring that each part meets its requirements and functions correctly. By isolating and testing these components, users can achieve more targeted verification, identify issues early, and improve the overall reliability and performance of the system.
Topics
- What Is Component Verification?
An overview of the two approaches to component verification.
- Generate Test Cases for a Subsystem
Analyze an individual subsystem.
- Generate Test Cases for a Reusable Library Subsystem
Analyze a reusable library subsystem.
- Achieve Missing Coverage in Subsystems and Model Blocks
Explains how to convert subsystems to Model blocks before attempting to achieve missing coverage.
- Use Test Generation Advisor to Identify Analyzable Components
Use the Test Generation Advisor to guide model and component analysis.
- Analyze a Stateflow Atomic Subchart
Analyzing an atomic subchart using Simulink Design Verifier software.
