This example shows what happens when a ramp signal is integrated using two resettable subsystems. After running the simulation, the scope shows three plots.
The middle plot shows the original value of the reset signal. In this example, we are using a discrete sample time pulse signal. The rising and falling edges are what cause the two subsystems to reset.
The top and bottom plots show the original ramp as a reference and its integration. The subsystems corresponding to the top and bottom plots reset on every rising and falling edge of the pulse, respectively. When each subsystem resets, the state of the integrator block is set to its initial condition value, which is 0. You can refer to the middle plot to determine when each subsystem resets.
Notice how the reset happens for blocks within the subsystem, without the need for each block to have its own reset port. This provides a more convenient way of handling reset at a subsystem level.