Main Content


Check whether signal is zero

  • Library:
  • Simulink / Model Verification

    HDL Coder / Model Verification

  • Assertion block


The Assertion block checks whether any of the elements of the input signal are zero. If all elements are nonzero, the block does nothing. If any element is zero, the block halts the simulation, by default, and displays an error message. Use the block parameter dialog box to:

  • Specify that the block displays a warning message when the assertion fails but allows the simulation to continue.

  • Specify a MATLAB® expression to evaluate when the assertion fails.

  • Enable or disable the assertion.

Use the blocks in the Model Verification library to facilitate creation of self-validating models. For example, you can use model verification blocks to test that signals do not exceed specified limits during simulation. When you are satisfied that a model is correct, you can turn error checking off by disabling the verification blocks. You do not have to remove them from the model. If you need to modify a model, you can temporarily turn the verification blocks back on to ensure that your changes do not break the model.



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Input signal to the assertion check.

Data Types: half | single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated


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Clearing this check box disables the block and causes the model to behave as if the block does not exist. You can set the Model Verification block enabling setting in the Configuration Parameters to enable or disable all model verification blocks in a model regardless of the setting of this option.

Command-Line Information

Parameter: enabled
Type: character vector
Values: 'on' | 'off'
Default: 'on'

Specify a MATLAB expression to evaluate when the assertion fails. Because the expression is evaluated in the MATLAB workspace, define all variables used in the expression in that workspace.

Command-Line Information

Parameter: callback
Type: character vector
Values: MATLAB expression
Default: ' '

Select this check box to indicate that the block halts simulation when the check fails. Clear to indicate that the software displays a warning and continues the simulation.

Command-Line Information

Parameter: stopWhenAssertionFail
Type: character vector
Values: 'on' | 'off'
Default: 'on'

Specify the sample time as a value other than -1. For more information, see Specify Sample Time.


This parameter is not visible unless it is explicitly set to a value other than -1. To learn more, see Blocks for Which Sample Time Is Not Recommended.

Programmatic Use

Block Parameter: SampleTime
Type: character vector
Values: scalar or vector
Default: '-1'

Block Characteristics

Data Types

Boolean | double | fixed point | half | integer | single

Direct Feedthrough


Multidimensional Signals


Variable-Size Signals


Zero-Crossing Detection


Extended Capabilities

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Introduced before R2006a