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SM AC8C

Discrete-time or continuous-time synchronous machine AC8C excitation system including an automatic voltage regulator and an exciter

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  • SM AC8C block

Description

The SM AC8C block implements a synchronous machine type AC8C excitation system model in conformance with IEEE 421.5-2016[1].

Use this block to model the control and regulation of the field voltage of a synchronous machine that operates as a generator using an AC rotating exciter.

You can switch between continuous and discrete implementations of the block by using the Sample time (-1 for inherited) parameter. To configure the integrator for continuous time, set the Sample time (-1 for inherited) property to 0. To configure the integrator for discrete time, set the Sample time (-1 for inherited) property to a positive, nonzero value, or to -1 to inherit the sample time from an upstream block.

The SM AC8C block is made up of five major components:

  • The Current Compensator modifies the measured terminal voltage as a function of the terminal current.

  • The Voltage Measurement Transducer simulates the dynamics of a terminal voltage transducer using a low-pass filter.

  • The Excitation Control Elements component compares the voltage transducer output with a terminal voltage reference to produce a voltage error. This voltage error is then passed through a voltage regulator to produce the exciter field voltage.

  • The AC Rotating Exciter models the AC rotating exciter, which produces a field voltage that is applied to the controlled synchronous machine. The block also feeds the exciter field current (which is given the standard symbol VFE) back to the excitation system.

  • The Power Source models the dependency of the power source for the controlled rectifier from the terminal voltage.

This diagram shows the overall structure of the AC8C excitation system model:

In the diagram:

  • VT and IT are the measured terminal voltage and current of the synchronous machine.

  • VC1 is the current-compensated terminal voltage.

  • VC is the filtered, current-compensated terminal voltage.

  • VREF is the reference terminal voltage.

  • VS is the power system stabilizer voltage.

  • SW1 is the user-selected power source switch for the controlled rectifier.

  • VB is the exciter field voltage.

  • EFE and VFE are the exciter field voltage and current, respectively.

  • EFD and IFD are the field voltage and current, respectively.

The following sections describe each of the major parts of the block in detail.

Current Compensator and Voltage Measurement Transducer

The current compensator is modeled as:

VC1=VT+ITRC2+XC2,

where:

  • RC is the load compensation resistance.

  • XC is the load compensation reactance.

The voltage measurement transducer is implemented as a Low-Pass Filter block with time constant TR. Refer to the documentation for this block for the discrete and continuous implementations.

Excitation Control Elements

This diagram illustrates the overall structure of the excitation control elements:

In the diagram:

  • The Summation Point Logic subsystem models the summation point input location for the overexcitation limiter (OEL), underexcitation limiter (UEL), stator current limiter (SCL), and the power switch selector (V_S) voltages. For more information about using limiters with this block, see Field Current Limiters.

  • There are two Take-over Logic subsystems. They model the take-over point input location for the OEL, UEL, SCL and PSS voltages. For more information about using limiters with this block, see Field Current Limiters.

  • The PID_R subsystem models a PID controller that functions as a control structure for the automatic voltage regulator. The minimum and maximum anti-windup saturation limits for the block are VPIDmin and VPIDmax, respectively.

  • The Low-Pass Filter block models the major dynamics of the voltage regulator. Here, KA is the regulator gain and TA is the major time constant of the regulator. The minimum and maximum anti-windup saturation limits for the block are VRmin and VRmax, respectively.

  • The Logical switch 1 parameter controls the origin of the power source for the controlled rectifier. The voltage regulator command signal VR is multiplied by the exciter field voltage, VB. For more information about the user-selected logical switch for the power source of the controlled rectifier, see Power Source.

Field Current Limiters

You can use various field current limiters to modify the output of the voltage regulator under unsafe operating conditions:

  • Use an overexcitation limiter to prevent overheating of the field winding due to excessive field current demand.

  • Use an underexcitation limiter to boost field excitation when it is too low, which risks desynchronization.

  • Use a stator current limiter to prevent overheating of the stator windings due to excessive current.

Attach the output of any of these limiters at one of these points:

  • The summation point as part of the automatic voltage regulator (AVR) feedback loop

  • The take-over point to override the usual behavior of the AVR

If you are using the stator current limiter at the summation point, use the single input VSCLsum. If you are using the stator current limiter at the take-over point, use both the overexcitation input, VOELscl, and the underexcitation input, VUELscl.

AC Rotating Exciter

This diagram illustrates the overall structure of the AC rotating exciter:

In the diagram:

  • The exciter field current VFE is modeled as the summation of three signals:

    • The nonlinear function Vx models the saturation of the exciter output voltage.

    • The proportional term KE models the linear relationship between exciter output voltage and the exciter field current.

    • The demagnetizing effect of the load current on the exciter output voltage is modeled using the demagnetization constant KD in the feedback loop.

  • The Integrator with variable limits subsystem integrates the difference between EFE and VFE to generate the exciter alternator output voltage VE. TE is the time constant for this process.

  • The nonlinear function FEX models the exciter output voltage drop from the rectifier regulation. This function depends on the constant KC, which itself is a function of commutating reactance.

  • The parameters VEmin and VFEmax model the lower and upper limits of the rotating exciter.

Power Source

It is possible to use different power source representations for the controlled rectifier by selecting the relevant option in the Logical switch 1 parameter. The power source for the controlled rectifier can be either derived from the terminal voltage (Position A: power source derived from terminal voltage) or it can be independent of the terminal voltage (Position B: power source independent from the terminal conditions).

Ports

Input

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Voltage regulator reference set point, in per-unit representation, specified as a scalar.

Data Types: single | double

Input from the power system stabilizer, in per-unit representation, specified as a scalar.

Data Types: single | double

Terminal voltage magnitude in per-unit representation, specified as a scalar.

Data Types: single | double

Terminal current magnitude in per-unit representation, specified as a scalar.

Data Types: single | double

Input from the overexcitation limiter, in per-unit representation, specified as a scalar.

Dependencies

  • To ignore the input from the overexcitation limiter, set Alternate OEL input locations (V_OEL) to Unused.

  • To use the input from the overexcitation limiter at the summation point, set Alternate OEL input locations (V_OEL) to Summation point.

  • To use the input from the overexcitation limiter at the take-over point, set Alternate OEL input locations (V_OEL) to Take-over.

Data Types: single | double

Input from the underexcitation limiter, in per-unit representation, specified as a scalar.

Dependencies

  • To ignore the input from the underexcitation limiter, set Alternate UEL input locations (V_UEL) to Unused.

  • To use the input from the underexcitation limiter at the summation point, set Alternate UEL input locations (V_UEL) to Summation point.

  • To use the input from the underexcitation limiter at the take-over point, set Alternate UEL input locations (V_UEL) to Take-over.

Data Types: single | double

Input from the stator current limiter when using the summation point, in per-unit representation, specified as a scalar.

Dependencies

  • To ignore the input from the stator current limiter, set Alternate SCL input locations (V_SCL) to Unused.

  • To use the input from the stator current limiter at the summation point, set Alternate SCL input locations (V_SCL) to Summation point.

Data Types: single | double

Input from the stator current limiter to prevent field overexcitation when using the take-over point, in per-unit representation, specified as a scalar.

Dependencies

  • To ignore the input from the stator current limiter, set Alternate SCL input locations (V_SCL) to Unused.

  • To use the input from the stator current limiter at the take-over point, set Alternate SCL input locations (V_SCL) to Take-over.

Data Types: single | double

Input from the stator current limiter to prevent field underexcitation when using the take-over point, in per-unit representation, specified as a scalar.

Dependencies

  • To ignore the input from the stator current limiter, set Alternate SCL input locations (V_SCL) to Unused.

  • To use the input from the stator current limiter at the take-over point, set Alternate SCL input locations (V_SCL) to Take-over.

Data Types: single | double

Measured per-unit field current of the synchronous machine, specified as a scalar.

Data Types: single | double

Output

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Per-unit field voltage to apply to the field circuit of the synchronous machine, returned as a scalar.

Data Types: single | double

Parameters

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General

Initial per-unit voltage to apply to the field circuit of the synchronous machine.

Initial per-unit voltage to apply to the terminal.

Initial per-unit voltage to apply to the terminal.

Time between consecutive block executions. During execution, the block produces outputs and, if appropriate, updates its internal state. For more information, see What Is Sample Time? and Specify Sample Time.

For inherited discrete-time operation, specify -1. For discrete-time operation, specify a positive integer. For continuous-time operation, specify 0.

If this block is in a masked subsystem, or other variant subsystem that allows you to switch between continuous operation and discrete operation, promote the sample time parameter. Promoting the sample time parameter ensures correct switching between the continuous and discrete implementations of the block. For more information, see Promote Parameter to Mask.

Pre-Control

Resistance used in the current compensation system. Set this parameter and Reactance component of load compensation, X_C (pu) to 0 to disable current compensation.

Reactance used in the current compensation system. Set this parameter and Resistive component of load compensation, R_C (pu) to 0 to disable current compensation.

Equivalent time constant for the voltage transducer filtering.

Control

Per-unit proportional gain of the voltage regulator.

Per-unit integral gain of the voltage regulator.

Derivative gain of the voltage regulator.

Equivalent lag time constant for the derivative channel of the PID controller.

Maximum admissible per-unit output of the PID regulator.

Minimum admissible per-unit output of the PID regulator.

Gain associated with the rectifier.

Time constant of the rectifier.

Maximum per-unit output voltage of the regulator.

Minimum per-unit output voltage of the regulator.

Location of the power system stabilizer input.

Location of the overexcitation limiter input.

Location of the underexcitation limiter input.

Location of the stator current limiter input:

  • If you select Summation point, use the V_SCLsum input port.

  • If you select any of the Take-over options, use the V_OELscl and V_UELscl input ports.

Exciter

Proportional constant for the exciter field.

Time constant for the exciter field.

Rectifier loading factor proportional to the commutating reactance.

Demagnetization factor related to the exciter alternator reactances.

Exciter output voltage for the first saturation factor.

Saturation factor for the first exciter.

Exciter output voltage for the second saturation factor.

Saturation factor for the second exciter.

Maximum per-unit field current limit reference.

Minimum per-unit exciter voltage output.

Per-unit potential circuit gain coefficient.

Dependencies

To enable this parameter, set Logical switch 1 to Position A: power source derived from terminal voltage.

Potential circuit phase angle, in degrees.

Dependencies

To enable this parameter, set Logical switch 1 to Position A: power source derived from terminal voltage.

Per-unit potential circuit current gain coefficient.

Dependencies

To enable this parameter, set Logical switch 1 to Position A: power source derived from terminal voltage.

Per-unit reactance associated with the potential source.

Dependencies

To enable this parameter, set Logical switch 1 to Position A: power source derived from terminal voltage.

Per-unit loading factor of the rectifier that is proportional to the commutating reactance.

Position of logical switch 1.

Maximum per-unit available field voltage for the exciter.

References

[1] IEEE Recommended Practice for Excitation System Models for Power System Stability Studies. IEEE Std 421.5-2016. Piscataway, NJ: IEEE-SA, 2016.

Extended Capabilities

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