Mixed-Signal Blockset™ provides models of components and impairments, analysis tools, and test benches for designing and verifying mixed-signal integrated circuits (ICs).
You can model PLLs, data converters, and other systems at different levels of abstraction. These models can be used to simulate mixed-signal components together with complex DSP algorithms and control logic. You can customize models to include impairments such as noise, nonlinearity, jitter, and quantization effects. Rapid system-level simulation using variable-step Simulink® solvers lets you debug the implementation and identify design flaws without simulating the IC at the transistor level.
With the Mixed-Signal Analyzer app you can analyze, identify trends in, and visualize mixed-signal data. The Cadence Virtuoso ADE MATLAB Integration option lets you import databases of circuit-level simulation results into MATLAB®. Alternatively, you can import a SPICE netlist and create or modify a linear, time-invariant circuit with parasitic elements extracted from the IC design. The blockset provides analysis functions for post-processing simulation results to verify specifications, fit characteristics, and report measurements.
This example shows how to design a simple phase-locked loop (PLL) using a reference architecture and validate it using PLL Testbench.
This example shows how to measure and analyze the effect of phase noise in a voltage controlled oscillator (VCO).
This example shows how to design a SAR ADC using reference architecture and validate the ADC using ADC Testbench.
This example shows how to design and evaluate a binary weighted DAC using reference architecture and validate the DAC using the DAC Testbench.