Default System with External DDR Memory Access Reference Design

With the HDL Coder™ software, you can generate an HDL IP core with AXI4 Master interfaces. Based on the target board, you can integrate this IP core with either an external PL DDR memory access reference design or a shared memory access reference design.

Reference Design that Access PL DDR External Memory

You can integrate the HDL IP core into the:

  • Default System with External DDR3 Memory Access reference design if you specify Xilinx Zynq ZC706 evaluation kit as the Target platform.

  • Default System with External DDR4 Memory Access reference design if you specify Xilinx Zynq UltraScale+ MPSoC ZCU102 evaluation kit as the Target platform.

  • Default system with External LPDDR4 Memory Access reference design if you specify Xilinx Versal AI Core Series VCK190 Evaluation Kit as the Target platform.

To use these reference designs, you must have HDL Verifier™ installed. This figure shows a high-level block diagram of the reference design architecture that access PL DDR external memory.

In this architecture, the HDL DUT IP block corresponds to the IP core that is generated from the IP Core Generation workflow. Other blocks in the architecture represent the predefined reference design, which consists of a MATLAB® based JTAG AXI Manager IP that is provided by HDL Verifier. After you run the FPGA design on the board, by using the JTAG AXI Manager IP, you can use the input data in MATLAB to initialize the on-board DDR external memory. The HDL DUT IP core reads the input data from the external memory via the AXI4 Master interface. The IP core then performs the algorithm computation and writes the result to DDR memory via the AXI4 Master interface. The JTAG AXI Manager IP can read the result from DDR memory, and then verify the result in MATLAB. If you specify Xilinx Zynq UltraScale+ MPSoC ZCU102 evaluation kit as the target platform, you can also tune the parameters in the HDL IP core by using the Zynq® processing system.

Reference Design that Access Shared DDR Memory

You can also integrate the HDL IP core to the Default system with Shared Memory Access reference design if you specify ZedBoard as the Target platform. To use this reference design, you do not require HDL Verifier.

In this architecture, the HDL DUT IP core is implemented in the programmable logic and communicates with the system shared DDR memory through an AXI4 Master interface. The IP core connects to the Zynq Processing System (PS) by using a high‑performance (HP) AXI slave port. The PS acts as an intermediary, routing AXI transactions from the Programmable Logic to the DDR memory controller, which manages access to the on‑board DDR.

Both the ARM® processor and the HDL IP core can access the shared DDR memory, enabling efficient data exchange between software and hardware. After you generate the FPGA design and program the board, you can use MATLAB to access and initialize the shared DDR memory. The HDL IP core reads the input data, processes the algorithm, and writes the results back to the shared DDR memory through the AXI4 Master interface. You can then read the results directly from the shared memory in MATLAB and verify the output.

Specifications

The specifications vary depending on the reference design that you specify to target the board.

Default System with External DDR3 Memory Access Reference Design

If you specify Xilinx Zynq ZC706 evaluation kit as the Target platform, you can target this reference design. The reference design specifications include:

  • Support for either AXI4 Master Read channel or AXI4 Master Write channel, or both AXI4 Master Read and AXI4 Master Write channels.

  • AXI4 Master Maximum Data bitwidth: 1024-bit

  • AXI4 Master Address bitwidth: 32-bit

For DUT IP core AXI4 Master interface:

  • DDR3 external memory address range: x40000000 to x7FFFFFFF

  • Default AXI4 Master Read channel base address: x40000000

  • Default AXI4 Master Write channel base address: x41000000

For MATLAB AXI Manager interface:

  • DDR3 external memory address range: x40000000 to x7FFFFFFF

  • DUT IP core base address: x00000000

Default System with External DDR4 Memory Access Reference Design

If you specify Xilinx Zynq UltraScale+ MPSoC ZCU102 evaluation kit as the Target platform, you can target this reference design. The reference design specifications include:

  • Support for either AXI4 Master Read channel or AXI4 Master Write channel, or both AXI4 Master Read and AXI4 Master Write channels.

  • AXI4 Master Maximum Data bitwidth: 1024-bit

  • AXI4 Master Address bitwidth: 32-bit

For DUT IP core AXI4 Master interface:

  • DDR4 external memory address range: x80000000 to x9FFFFFFF

  • Default AXI4 Master Read channel base address: x80000000

  • Default AXI4 Master Write channel base address: x90000000

For MATLAB AXI Manager interface:

  • DDR4 external memory address range: x80000000 to x9FFFFFFF

  • DUT IP core base address: xA0000000

Default System with External LPDDR4 Memory Access Reference Design

Since R2025a

If you specify Xilinx Versal AI Core Series VCK190 Evaluation Kit as the Target platform, you can target this reference design. The reference design specifications include:

  • Support for either AXI4 Master Read channel or AXI4 Master Write channel, or both AXI4 Master Read and AXI4 Master Write channels.

  • AXI4 Master Maximum Data bitwidth: 1024-bit

  • AXI4 Master Address bitwidth: 64-bit

For DUT IP core AXI4 Master interface:

  • LPDDR4 external memory address range: 0x50000000000 to 0x501FFFFFFFF

  • Default AXI4 Master Read channel base address: 50000000000

  • Default AXI4 Master Write channel base address: 50100000000

For MATLAB AXI Manager interface:

  • DDR4 external memory address range: 0x50000000000 to 0x501FFFFFFFF

  • DUT IP core base address: xA4000000

Default System with Shared Memory Access Reference Design

Since R2026a

If you specify ZedBoard as the Target platform, you can target this reference design. The reference design specifications include:

  • Support for either AXI4 Master Read channel or AXI4 Master Write channel, or both AXI4 Master Read and AXI4 Master Write channels.

  • AXI4 Master Maximum Data bitwidth: 1024-bit

  • AXI4 Master Address bitwidth: 32-bit

For DUT IP core AXI4 Master interface:

  • Shared memory address range: 0x10000000 to 0x18000000

  • Default AXI4 Master Read channel base address: 10000000

  • Default AXI4 Master Write channel base address: 14000000

Targeting the Reference Design

To target your algorithm in Simulink® to the reference designs:

  1. Model your algorithm with the simplified AXI4 Master protocol. To generate an IP core with AXI4 Master interfaces, in your DUT interface, implement the Data signals and AXI4 Master Read and AXI4 Master Write controls signals as a bus. For more information, see Model Design for AXI4 Master Interface Generation.

  2. Open the HDL Workflow Advisor. In the Set Target Device and Synthesis Tool task, specify IP Core Generation as the Target workflow. For Target platform, select Xilinx Zynq ZC706 evaluation kit or Xilinx Zynq UltraScale+ MPSoC ZCU102 evaluation kit.

  3. In the Set Target Reference Design task, for Reference design, specify Default System with External DDR3 Memory Access. If you specified Xilinx Zynq UltraScale+ MPSoC ZCU102 evaluation kit as the target platform, you can select Default System with External DDR3 Memory Access as the target platform.

Go through the workflow to generate the HDL IP core, and integrate the IP core into the target reference design.

Board Support

You can use the Default System with External DDR Memory Access reference design architecture with these target platforms:

  • Xilinx® Zynq ZC706 evaluation kit

  • Xilinx Zynq UltraScale+™ MPSoC ZCU102 evaluation kit

  • Xilinx Versal® AI Core Series VCK190 evaluation kit

To use Default System with Shared Memory Access reference design architecture, set the target platform to ZedBoard™.

See Also

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